Fix type(typedef) operation core dump

src/V3Width.cpp

@@ -1735,12 +1735,19 @@ private:
         if (nodep->didWidthAndSet()) return;  // This node is a dtype & not both PRELIMed+FINALed
         nodep->doingWidth(true);
         if (nodep->typeofp()) {  // type(typeofp_expression)
-            // Type comes from expression's type
-            userIterateAndNext(nodep->typeofp(), WidthVP{SELF, BOTH}.p());
-            AstNode* const typeofp = nodep->typeofp();
-            nodep->typedefp(nullptr);
-            nodep->refDTypep(typeofp->dtypep());
-            VL_DO_DANGLING(typeofp->unlinkFrBack()->deleteTree(), typeofp);
+            if (AstNodeDType* typeofDtp = VN_CAST(nodep->typeofp(), NodeDType)) {
+                // It's directly a type, e.g. "type(int)"
+                typeofDtp = iterateEditMoveDTypep(nodep, typeofDtp);  // Changes typeofp
+                nodep->typedefp(nullptr);
+                nodep->refDTypep(typeofDtp);
+            } else {
+                // Type comes from expression's type, e.g. "type(variable)"
+                userIterateAndNext(nodep->typeofp(), WidthVP{SELF, BOTH}.p());
+                AstNode* const typeofp = nodep->typeofp();
+                nodep->typedefp(nullptr);
+                nodep->refDTypep(typeofp->dtypep());
+                VL_DO_DANGLING(typeofp->unlinkFrBack()->deleteTree(), typeofp);
+            }
             // We had to use AstRefDType for this construct as pointers to this type
             // in type table are still correct (which they wouldn't be if we replaced the node)
         }

test_regress/t/t_param_type_bit.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;

test_regress/t/t_param_type_bit.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This test examines Verilator against paramter definition with functions.
+// Particularly the function takes in argument which is multi-dimentional.
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   sub sub();
+endmodule
+
+module sub
+  #(parameter type T = type(bit[9:0]) )
+   ();
+
+   type(bit[9:0]) tvar;
+
+   initial begin
+      if ($bits(T) != 10) $stop;
+      if ($bits(tvar) != 10) $stop;
+      $finish;
+   end
+endmodule