Tests: Fix some force/release coverage holes.

test_regress/t/t_debug_emitv.out

@@ -328,9 +328,19 @@ module Vt_debug_emitv_t;
             $display("%g", $asinh(r));
             $display("%g", $acosh(r));
             $display("%g", $atanh(r));
+            force sum = 'sha;
+            __Vrepeat0 = 'sh2;
+            while ((__Vrepeat0 > 32'h0)) begin
+                if ((sum != 'sha)) begin
+                    $stop;
+                end
+                __Vrepeat0 = (__Vrepeat0 - 32'h1);
+            end
+            release sum;
         end
     end
     /*verilator public_flat_rw @(posedge clk) pubflat*/
+    signed integer [31:0]  __Vrepeat0;
 endmodule
 package Vt_debug_emitv___024unit;
     class Vt_debug_emitv_Cls;

test_regress/t/t_debug_emitv.v

@@ -197,6 +197,10 @@ module t (/*AUTOARG*/
       $display("%g", $asinh(r));
       $display("%g", $acosh(r));
       $display("%g", $atanh(r));
+
+      force sum = 10;
+      repeat (2) if (sum != 10) $stop;
+      release sum;
    end
 endmodule
 

test_regress/t/t_force_bad_rw.out

@@ -0,0 +1,5 @@
+%Error: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced
+                                : ... In instance t.unnamedblk1.index
+   14 |       foreach (ass[index]) begin
+      |                    ^~~~~
+%Error: Exiting due to

test_regress/t/t_force_bad_rw.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_force_bad_rw.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   int ass[int];
+
+   initial begin
+      ass[2] = 20;
+
+      foreach (ass[index]) begin
+         force index = 0;
+         $display("ii %d\n", index);
+      end
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule