Add error to avoid @* fatal

src/V3Timing.cpp

@@ -541,6 +541,7 @@ private:
     void visit(AstEventControl* nodep) override {
         // Do not allow waiting on local named events, as they get enqueued for clearing, but can
         // go out of scope before that happens
+        if (!nodep->sensesp()) nodep->v3warn(E_UNSUPPORTED, "Unsupported: no sense equation (@*)");
         if (nodep->sensesp()->exists([](const AstNodeVarRef* refp) {
                 AstBasicDType* const dtypep = refp->dtypep()->skipRefp()->basicp();
                 return dtypep && dtypep->isEvent() && refp->varp()->isFuncLocal();

test_regress/t/t_event_control_star.out

@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_event_control_star.v:19:14: Unsupported: no sense equation (@*)
+   19 |      @* a = c;   
+      |              ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
+%Error: Command Failed

test_regress/t/t_event_control_star.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--timing"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_event_control_star.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// Based on ivtest's nested_impl_event1.v by Martin Whitaker.
+
+module t();
+
+   reg a;
+   reg b;
+   reg c;
+
+   always @* begin  // @(b or c)
+     a = b;
+     $display("[%0t] Triggered 1 @(b or c)", $time);
+
+     @* a = c;  // @(c)
+     $display("[%0t] Triggered 2 @(c)", $time);
+   end
+
+   initial begin
+      #10;
+      b = 0;
+      #10;
+      b = 1;
+      #10;
+      c = 0;
+      #10;
+      c = 1;
+      #10;
+      c = 0;
+      #10;
+      $write("*-* All Finished *-*\n");
+      $finish(0);
+   end
+
+endmodule