forked from github/verilator
Internals: add const
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@ -5497,7 +5497,7 @@ private:
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} else {
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userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
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if (nodep->edgeType().anEdge()) {
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AstNodeDType* sensDtp = nodep->sensp()->dtypep()->skipRefp();
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AstNodeDType* const sensDtp = nodep->sensp()->dtypep()->skipRefp();
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if (sensDtp->isDouble()) {
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nodep->sensp()->v3error(
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"Edge event control not legal on real type (IEEE 1800-2017 6.12.1)");
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