Fix fclose(0).

src/V3AstNodeExpr.h

@@ -1109,6 +1109,7 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
     int instrCount() const override { return widthInstrs() * 64; }
+    bool isPredictOptimizable() const override { return false; }
     bool isPure() const override { return false; }  // SPECIAL: $display has 'visual' ordering
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
@@ -2404,6 +2405,7 @@ public:
     bool sizeMattersLhs() const override { return false; }
     bool sizeMattersRhs() const override { return false; }
     int instrCount() const override { return widthInstrs() * 64; }
+    bool isPredictOptimizable() const override { return false; }
     bool isPure() const override { return false; }  // SPECIAL: $display has 'visual' ordering
     AstNode* filep() const { return lhsp(); }
     AstNode* charp() const { return rhsp(); }

src/V3EmitCFunc.h

@@ -715,8 +715,6 @@ public:
         puts("VL_FCLOSE_I(");
         iterateAndNextNull(nodep->filep());
         puts("); ");
-        iterateAndNextNull(nodep->filep());  // For safety, so user doesn't later WRITE with it.
-        puts(" = 0;\n");
     }
     void visit(AstFFlush* nodep) override {
         if (!nodep->filep()) {

test_regress/t/t_sys_file_basic.v

@@ -74,10 +74,7 @@ module t;
       $fflush;
 
       $fclose(file);
-`ifdef verilator
-      if (file != 0) $stop(1);  // Also test arguments to stop
       $fwrite(file, "Never printed, file closed\n");
-`endif
 
       begin
          // Check for opening errors

test_regress/t/t_sys_file_zero.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_sys_file_zero.v

@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t;
+   int i;
+   int v;
+   string s;
+   reg [100*8:1]  letterl;
+
+   initial begin
+      // Display formatting
+      $fwrite(0, "Never printed, file closed\n");
+      i = $feof(0);
+      if (i == 0) $stop;
+      $fflush(0);
+      $fclose(0);
+      i = $ferror(0, letterl);
+      i = $fgetc(0);
+      `checkd(i, -1);
+      i = $ungetc(0, 0);
+      `checkd(i, -1);
+      i = $fgets(letterl, 0);
+      `checkd(i, 0);
+      i = $fscanf(0, "%x", v);
+      `checkd(i, -1);
+      i = $ftell(0);
+      `checkd(i, -1);
+      i = $rewind(0);
+      `checkd(i, -1);
+      i = $fseek(0, 10, 0);
+      `checkd(i, -1);
+
+      $write("*-* All Finished *-*\n");
+      $finish(0);  // Test arguments to finish
+   end
+
+endmodule