forked from github/verilator
Fix duplicate typedefs in generate for, #2205.
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@ -17,6 +17,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix packages as enum base types, #2202. [Driss Hafdi]
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**** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc]
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* Verilator 4.030 2020-03-08
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@ -167,6 +167,18 @@ private:
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else m_modp->addStmtp(nodep);
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}
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}
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virtual void visit(AstTypedef* nodep) VL_OVERRIDE {
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if (m_unnamedScope != "") {
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// Rename it
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nodep->name(m_unnamedScope + "__DOT__" + nodep->name());
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m_statep->userMarkChanged(nodep);
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// Move to module
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nodep->unlinkFrBack();
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// Begins under funcs just move into the func
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if (m_ftaskp) m_ftaskp->addStmtsp(nodep);
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else m_modp->addStmtp(nodep);
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}
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}
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virtual void visit(AstCell* nodep) VL_OVERRIDE {
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UINFO(8," CELL "<<nodep<<endl);
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if (m_namedScope != "") {
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16
test_regress/t/t_struct_genfor.pl
Executable file
16
test_regress/t/t_struct_genfor.pl
Executable file
@ -0,0 +1,16 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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lint();
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ok(1);
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1;
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25
test_regress/t/t_struct_genfor.v
Normal file
25
test_regress/t/t_struct_genfor.v
Normal file
@ -0,0 +1,25 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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for (genvar g = 0; g < 2; ++g) begin : genfor
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typedef struct packed {
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logic [31:0] val1;
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logic [31:0] val2;
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} struct_t;
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struct_t forvar;
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initial begin
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forvar.val1 = 1;
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forvar.val2 = 2;
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if (forvar.val1 != 1) $stop;
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if (forvar.val2 != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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