Fix duplicate typedefs in generate for, #2205.

This commit is contained in:
Wilson Snyder 2020-03-26 18:10:20 -04:00
parent 590b1853d0
commit 4145a38c47
4 changed files with 55 additions and 0 deletions

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@ -17,6 +17,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix packages as enum base types, #2202. [Driss Hafdi]
**** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc]
* Verilator 4.030 2020-03-08

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@ -167,6 +167,18 @@ private:
else m_modp->addStmtp(nodep);
}
}
virtual void visit(AstTypedef* nodep) VL_OVERRIDE {
if (m_unnamedScope != "") {
// Rename it
nodep->name(m_unnamedScope + "__DOT__" + nodep->name());
m_statep->userMarkChanged(nodep);
// Move to module
nodep->unlinkFrBack();
// Begins under funcs just move into the func
if (m_ftaskp) m_ftaskp->addStmtsp(nodep);
else m_modp->addStmtp(nodep);
}
}
virtual void visit(AstCell* nodep) VL_OVERRIDE {
UINFO(8," CELL "<<nodep<<endl);
if (m_namedScope != "") {

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@ -0,0 +1,16 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint();
ok(1);
1;

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@ -0,0 +1,25 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t ();
for (genvar g = 0; g < 2; ++g) begin : genfor
typedef struct packed {
logic [31:0] val1;
logic [31:0] val2;
} struct_t;
struct_t forvar;
initial begin
forvar.val1 = 1;
forvar.val2 = 2;
if (forvar.val1 != 1) $stop;
if (forvar.val2 != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule