forked from github/verilator
Fix packages as enum base types, #2202.
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@ -15,6 +15,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix VCD open with empty filename, #2198. [Julius Baxter]
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**** Fix packages as enum base types, #2202. [Driss Hafdi]
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* Verilator 4.030 2020-03-08
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@ -1788,7 +1788,12 @@ enum_base_typeE<dtypep>: // IEEE: enum_base_type
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| integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1,$3,true); }
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// // below can be idAny or yaID__aTYPE
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// // IEEE requires a type, though no shift conflict if idAny
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| idAny rangeListE { $$ = GRAMMARP->createArray(new AstRefDType($<fl>1, *$1), $2, true); }
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// // IEEE: type_identifier [ packed_dimension ]
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// // however other simulators allow [ class_scope | package_scope ] type_identifier
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| idAny rangeListE
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{ $$ = GRAMMARP->createArray(new AstRefDType($<fl>1, *$1), $2, true); }
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| package_scopeIdFollows idRefDType rangeListE
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{ $2->packagep($1); $$ = GRAMMARP->createArray($2, $3, true); }
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;
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enum_nameList<nodep>:
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21
test_regress/t/t_typedef_package.pl
Executable file
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test_regress/t/t_typedef_package.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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24
test_regress/t/t_typedef_package.v
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24
test_regress/t/t_typedef_package.v
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@ -0,0 +1,24 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Driss Hafdi.
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// SPDX-License-Identifier: CC0-1.0
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package pkg1;
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typedef logic [7:0] uint8_t;
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endpackage
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package pkg2;
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typedef enum pkg1::uint8_t {
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a = 8'd1,
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b = 8'd2
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} opts;
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endpackage
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module t (/*AUTOARG*/);
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initial begin
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$display("%d", pkg2::a);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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