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Tests: Standardize verilog indentation.

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This commit is contained in:
Wilson Snyder 2020-04-05 21:53:24 -04:00
parent 50535a1894
commit 383f9832d4
6 changed files with 31 additions and 29 deletions
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16
examples/make_protect_lib/secret_impl.v
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@ -6,14 +6,16 @@
// This module will be used as libsecret.a or libsecret.so without // This module will be used as libsecret.a or libsecret.so without
// exposing the source. // exposing the source.
module secret_impl(
input [31:0] a,
input [31:0] b,
output logic [31:0] x,
input clk);
logic [31:0] accum_q = 0; module secret_impl
logic [31:0] secret_value = 9; (
input [31:0] a,
input [31:0] b,
output logic [31:0] x,
input clk);
logic [31:0] accum_q = 0;
logic [31:0] secret_value = 9;
initial $display("%m: initialized"); initial $display("%m: initialized");

10
examples/make_tracing_c/top.v
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@ -11,15 +11,15 @@
module top module top
( (
// Declare some signals so we can see how I/O works // Declare some signals so we can see how I/O works
input clk, input clk,
input reset_l, input reset_l,
output wire [1:0] out_small, output wire [1:0] out_small,
output wire [39:0] out_quad, output wire [39:0] out_quad,
output wire [69:0] out_wide, output wire [69:0] out_wide,
input [1:0] in_small, input [1:0] in_small,
input [39:0] in_quad, input [39:0] in_quad,
input [69:0] in_wide input [69:0] in_wide
); );
// Connect up the outputs, using some trivial logic // Connect up the outputs, using some trivial logic

12
examples/make_tracing_sc/top.v
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@ -11,16 +11,16 @@
module top module top
( (
// Declare some signals so we can see how I/O works // Declare some signals so we can see how I/O works
input clk, input clk,
input fastclk, input fastclk,
input reset_l, input reset_l,
output wire [1:0] out_small, output wire [1:0] out_small,
output wire [39:0] out_quad, output wire [39:0] out_quad,
output wire [69:0] out_wide, output wire [69:0] out_wide,
input [1:0] in_small, input [1:0] in_small,
input [39:0] in_quad, input [39:0] in_quad,
input [69:0] in_wide input [69:0] in_wide
); );
// Connect up the outputs, using some trivial logic // Connect up the outputs, using some trivial logic

2
examples/xml_py/sub.v
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@ -8,7 +8,7 @@
module sub module sub
#(parameter type TYPE_t = logic) #(parameter type TYPE_t = logic)
( (
input TYPE_t in, input TYPE_t in,
output TYPE_t out output TYPE_t out
); );

12
examples/xml_py/top.v
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@ -7,16 +7,16 @@
module top module top
( (
input clk, input clk,
input fastclk, input fastclk,
input reset_l, input reset_l,
output wire [1:0] out_small, output wire [1:0] out_small,
output wire [39:0] out_quad, output wire [39:0] out_quad,
output wire [69:0] out_wide, output wire [69:0] out_wide,
input [1:0] in_small, input [1:0] in_small,
input [39:0] in_quad, input [39:0] in_quad,
input [69:0] in_wide input [69:0] in_wide
); );
sub #(.TYPE_t(logic [1:0])) sub_small sub #(.TYPE_t(logic [1:0])) sub_small

8
test_regress/t/t_EXAMPLE.v
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@ -22,12 +22,12 @@ module t(/*AUTOARG*/
); );
input clk; input clk;
integer cyc=0; integer cyc=0;
reg [63:0] crc; reg [63:0] crc;
reg [63:0] sum; reg [63:0] sum;
// Take CRC data and apply to testblock inputs // Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0]; wire [31:0] in = crc[31:0];
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)