From 383f9832d4f9e2ef1425388e3c352d639539be82 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 5 Apr 2020 21:53:24 -0400 Subject: [PATCH] Tests: Standardize verilog indentation. --- examples/make_protect_lib/secret_impl.v | 16 +++++++++------- examples/make_tracing_c/top.v | 10 +++++----- examples/make_tracing_sc/top.v | 12 ++++++------ examples/xml_py/sub.v | 2 +- examples/xml_py/top.v | 12 ++++++------ test_regress/t/t_EXAMPLE.v | 8 ++++---- 6 files changed, 31 insertions(+), 29 deletions(-) diff --git a/examples/make_protect_lib/secret_impl.v b/examples/make_protect_lib/secret_impl.v index fd8557af1..1e39257f5 100644 --- a/examples/make_protect_lib/secret_impl.v +++ b/examples/make_protect_lib/secret_impl.v @@ -6,14 +6,16 @@ // This module will be used as libsecret.a or libsecret.so without // exposing the source. -module secret_impl( - input [31:0] a, - input [31:0] b, - output logic [31:0] x, - input clk); - logic [31:0] accum_q = 0; - logic [31:0] secret_value = 9; +module secret_impl + ( + input [31:0] a, + input [31:0] b, + output logic [31:0] x, + input clk); + + logic [31:0] accum_q = 0; + logic [31:0] secret_value = 9; initial $display("%m: initialized"); diff --git a/examples/make_tracing_c/top.v b/examples/make_tracing_c/top.v index a11027546..dbc852814 100644 --- a/examples/make_tracing_c/top.v +++ b/examples/make_tracing_c/top.v @@ -11,15 +11,15 @@ module top ( // Declare some signals so we can see how I/O works - input clk, - input reset_l, + input clk, + input reset_l, output wire [1:0] out_small, output wire [39:0] out_quad, output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide ); // Connect up the outputs, using some trivial logic diff --git a/examples/make_tracing_sc/top.v b/examples/make_tracing_sc/top.v index 534acb8e1..a31254951 100644 --- a/examples/make_tracing_sc/top.v +++ b/examples/make_tracing_sc/top.v @@ -11,16 +11,16 @@ module top ( // Declare some signals so we can see how I/O works - input clk, - input fastclk, - input reset_l, + input clk, + input fastclk, + input reset_l, output wire [1:0] out_small, output wire [39:0] out_quad, output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide ); // Connect up the outputs, using some trivial logic diff --git a/examples/xml_py/sub.v b/examples/xml_py/sub.v index ba2eed35c..67b577285 100644 --- a/examples/xml_py/sub.v +++ b/examples/xml_py/sub.v @@ -8,7 +8,7 @@ module sub #(parameter type TYPE_t = logic) ( - input TYPE_t in, + input TYPE_t in, output TYPE_t out ); diff --git a/examples/xml_py/top.v b/examples/xml_py/top.v index 405bf46c5..1106464f1 100644 --- a/examples/xml_py/top.v +++ b/examples/xml_py/top.v @@ -7,16 +7,16 @@ module top ( - input clk, - input fastclk, - input reset_l, + input clk, + input fastclk, + input reset_l, output wire [1:0] out_small, output wire [39:0] out_quad, output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide ); sub #(.TYPE_t(logic [1:0])) sub_small diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index befacfb1a..4e1051614 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -22,12 +22,12 @@ module t(/*AUTOARG*/ ); input clk; - integer cyc=0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire [31:0] in = crc[31:0]; + wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs)