diff --git a/Changes b/Changes
index 00872b6b8..c479df409 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix interface ports with comma lists, msg1058. [Ed Lander]
 
+****  Fix parameter real conversion from integer.
+
 ****  Fix clang warnings, bug668.  [Yutetsu Takatsukasa]
 
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index ca64a072e..813c2937f 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -915,6 +915,9 @@ private:
 	    if (!nodep->valuep()->castInitArray()) { // No dtype at present, perhaps TODO
 		widthCheck(nodep,"Initial value",nodep->valuep(),nodep->width(),nodep->widthMin());
 	    }
+	    if (nodep->isDouble() && !nodep->valuep()->isDouble()) {
+		spliceCvtD(nodep->valuep());
+	    }
 	}
 	UINFO(4,"varWidthed "<<nodep<<endl);
 	//if (debug()) nodep->dumpTree(cout,"  InitOut: ");
diff --git a/test_regress/t/t_vams_wreal.pl b/test_regress/t/t_vams_wreal.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_vams_wreal.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v
new file mode 100644
index 000000000..091c792c2
--- /dev/null
+++ b/test_regress/t/t_vams_wreal.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+`begin_keywords "VAMS-2.3"
+
+module t (/*autoarg*/
+   // Outputs
+   aout,
+   // Inputs
+   in
+   );
+
+   input [15:0] in;
+   output 	aout; 
+   wreal aout;
+
+   parameter real lsb = 1;
+   // verilator lint_off WIDTH
+   assign  aout = $itor(in) * lsb;
+   
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule