Fix info message prints under --assert (#4036) (#4053)

docs/CONTRIBUTORS

@@ -127,6 +127,7 @@ Samuel Riedel
 Sean Cross
 Sebastien Van Cauwenberghe
 Sergi Granell
+Srinivasan Venkataramanan
 Stefan Wallentowitz
 Stephen Henry
 Steven Hugg

src/V3Assert.cpp

@@ -51,14 +51,22 @@ private:
     bool m_inSampled = false;  // True inside a sampled expression
 
     // METHODS
-    string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message) {
+    string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message,
-        return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+                                VDisplayType severity) {
-                + cvtToStr(nodep->fileline()->lineno()) + ": Assertion failed in %m"
+        if (severity == VDisplayType::DT_ERROR || severity == VDisplayType::DT_FATAL) {
-                + ((message != "") ? ": " : "") + message + "\n");
+            return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+                    + cvtToStr(nodep->fileline()->lineno()) + ": Assertion failed in %m"
+                    + ((message != "") ? ": " : "") + message + "\n");
+        } else {
+            return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+                    + cvtToStr(nodep->fileline()->lineno()) + ": %m"
+                    + ((message != "") ? ": " : "") + message + "\n");
+        }
     }
     void replaceDisplay(AstDisplay* nodep, const string& prefix) {
+        nodep->fmtp()->text(
+            assertDisplayMessage(nodep, prefix, nodep->fmtp()->text(), nodep->displayType()));
         nodep->displayType(VDisplayType::DT_WRITE);
-        nodep->fmtp()->text(assertDisplayMessage(nodep, prefix, nodep->fmtp()->text()));
         // cppcheck-suppress nullPointer
         AstNodeExpr* const timenewp = new AstTime{nodep->fileline(), m_modp->timeunit()};
         if (AstNodeExpr* const timesp = nodep->fmtp()->exprsp()) {
@@ -419,9 +427,10 @@ private:
             replaceDisplay(nodep, "-Info");
         } else if (nodep->displayType() == VDisplayType::DT_WARNING) {
             replaceDisplay(nodep, "%%Warning");
-        } else if (nodep->displayType() == VDisplayType::DT_ERROR
+        } else if (nodep->displayType() == VDisplayType::DT_ERROR) {
-                   || nodep->displayType() == VDisplayType::DT_FATAL) {
             replaceDisplay(nodep, "%%Error");
+        } else if (nodep->displayType() == VDisplayType::DT_FATAL) {
+            replaceDisplay(nodep, "%%Fatal");
         } else if (nodep->displayType() == VDisplayType::DT_MONITOR) {
             nodep->displayType(VDisplayType::DT_DISPLAY);
             const auto fl = nodep->fileline();

test_regress/t/t_assert_synth.v

@@ -111,4 +111,9 @@ module t (/*AUTOARG*/
       end
    end
 
+  initial begin : test_info
+    $info ("Start of $info test");
+    $info ("Middle of $info test");
+    $info ("End of $info test");
+  end : test_info
 endmodule

test_regress/t/t_assert_synth_full.out

@@ -1,3 +1,6 @@
+[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
+[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
+[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
 [40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found
 %Error: t/t_assert_synth.v:31: Verilog $stop
 Aborting...

test_regress/t/t_assert_synth_full_vlt.out

@@ -1,3 +1,6 @@
+[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
+[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
+[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
 [40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found
 %Error: t/t_assert_synth.v:40: Verilog $stop
 Aborting...

test_regress/t/t_assert_synth_parallel.out

@@ -1,3 +1,6 @@
+[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
+[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
+[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
 [40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
 %Error: t/t_assert_synth.v:50: Verilog $stop
 Aborting...

test_regress/t/t_assert_synth_parallel_vlt.out

@@ -1,3 +1,6 @@
+[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
+[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
+[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
 [40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
 %Error: t/t_assert_synth.v:55: Verilog $stop
 Aborting...