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Fix info message prints under --assert (#4036) (#4053)

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Srinivasan Venkataramanan 2023-03-24 19:22:48 -04:00 committed by Wilson Snyder
parent 14c8f072f1
commit 2290e6ccf2
7 changed files with 34 additions and 7 deletions
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1
docs/CONTRIBUTORS
View File

@ -127,6 +127,7 @@ Samuel Riedel
Sean Cross
Sebastien Van Cauwenberghe
Sergi Granell
Srinivasan Venkataramanan
Stefan Wallentowitz
Stephen Henry
Steven Hugg

23
src/V3Assert.cpp
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@ -51,14 +51,22 @@ private:
bool m_inSampled = false; // True inside a sampled expression
// METHODS
string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message) {
return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+ cvtToStr(nodep->fileline()->lineno()) + ": Assertion failed in %m"
+ ((message != "") ? ": " : "") + message + "\n");
string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message,
VDisplayType severity) {
if (severity == VDisplayType::DT_ERROR || severity == VDisplayType::DT_FATAL) {
return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+ cvtToStr(nodep->fileline()->lineno()) + ": Assertion failed in %m"
+ ((message != "") ? ": " : "") + message + "\n");
} else {
return (string("[%0t] " + prefix + ": ") + nodep->fileline()->filebasename() + ":"
+ cvtToStr(nodep->fileline()->lineno()) + ": %m"
+ ((message != "") ? ": " : "") + message + "\n");
}
}
void replaceDisplay(AstDisplay* nodep, const string& prefix) {
nodep->fmtp()->text(
assertDisplayMessage(nodep, prefix, nodep->fmtp()->text(), nodep->displayType()));
nodep->displayType(VDisplayType::DT_WRITE);
nodep->fmtp()->text(assertDisplayMessage(nodep, prefix, nodep->fmtp()->text()));
// cppcheck-suppress nullPointer
AstNodeExpr* const timenewp = new AstTime{nodep->fileline(), m_modp->timeunit()};
if (AstNodeExpr* const timesp = nodep->fmtp()->exprsp()) {
@ -419,9 +427,10 @@ private:
replaceDisplay(nodep, "-Info");
} else if (nodep->displayType() == VDisplayType::DT_WARNING) {
replaceDisplay(nodep, "%%Warning");
} else if (nodep->displayType() == VDisplayType::DT_ERROR
|| nodep->displayType() == VDisplayType::DT_FATAL) {
} else if (nodep->displayType() == VDisplayType::DT_ERROR) {
replaceDisplay(nodep, "%%Error");
} else if (nodep->displayType() == VDisplayType::DT_FATAL) {
replaceDisplay(nodep, "%%Fatal");
} else if (nodep->displayType() == VDisplayType::DT_MONITOR) {
nodep->displayType(VDisplayType::DT_DISPLAY);
const auto fl = nodep->fileline();

5
test_regress/t/t_assert_synth.v
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@ -111,4 +111,9 @@ module t (/*AUTOARG*/
end
end
initial begin : test_info
$info ("Start of $info test");
$info ("Middle of $info test");
$info ("End of $info test");
end : test_info
endmodule

3
test_regress/t/t_assert_synth_full.out
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@ -1,3 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found
%Error: t/t_assert_synth.v:31: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_full_vlt.out
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@ -1,3 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found
%Error: t/t_assert_synth.v:40: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_parallel.out
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@ -1,3 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_synth.v:50: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_parallel_vlt.out
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@ -1,3 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_synth.v:55: Verilog $stop
Aborting...