forked from github/verilator
Internals: Remove dead code. No functional change intended.
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2e26e44538
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@ -46,8 +46,6 @@ class InstVisitor : public AstNVisitor {
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private:
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// NODE STATE
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// Cleared each Cell:
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// AstVar::user1p() -> AstNode*. Expression connected to given pin
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// AstVarRef::user1p() -> bool. True if created senitem for parent's connected signal
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// AstPin::user1p() -> bool. True if created assignment already
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AstUser1InUse m_inuser1;
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@ -75,10 +73,6 @@ private:
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m_cellp = nodep;
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//VV***** We reset user1p() on each cell!!!
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AstNode::user1ClearTree();
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// Collect pin expressions, so submod->varp->user1p() points to expression it connects to
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for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
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pinp->modVarp()->user1p(pinp->exprp());
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}
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nodep->iterateChildren(*this);
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m_cellp = NULL;
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}
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@ -29,9 +29,9 @@ module t (/*AUTOARG*/
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// Test loop
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always @ (posedge clk) begin
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//`ifdef TEST_VERBOSE
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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//`endif
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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