diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 9c217ce5b..31d2cdfc6 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -46,8 +46,6 @@ class InstVisitor : public AstNVisitor {
 private:
     // NODE STATE
     // Cleared each Cell:
-    //  AstVar::user1p()	-> AstNode*.  Expression connected to given pin
-    //  AstVarRef::user1p()	-> bool.  True if created senitem for parent's connected signal
     //  AstPin::user1p()	-> bool.  True if created assignment already
     AstUser1InUse	m_inuser1;
 
@@ -75,10 +73,6 @@ private:
 	m_cellp = nodep;
 	//VV*****  We reset user1p() on each cell!!!
 	AstNode::user1ClearTree();
-	// Collect pin expressions, so submod->varp->user1p() points to expression it connects to
-	for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
-	    pinp->modVarp()->user1p(pinp->exprp());
-	}
 	nodep->iterateChildren(*this);
 	m_cellp = NULL;
     }
diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v
index d7026e6ed..8926ae8ee 100644
--- a/test_regress/t/t_func_return.v
+++ b/test_regress/t/t_func_return.v
@@ -29,9 +29,9 @@ module t (/*AUTOARG*/
 
    // Test loop
    always @ (posedge clk) begin
-//`ifdef TEST_VERBOSE
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
-//`endif
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};