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Support $stable

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This commit is contained in:
Wilson Snyder 2020-08-23 11:34:19 -04:00
parent d2fac4aa2f
commit 1dce6b2500
8 changed files with 30 additions and 2 deletions
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1
src/verilog.l
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@ -420,6 +420,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<S05,S09,S12,S17,SAX>{
/* System Tasks */
"$bits" { FL; return yD_BITS; }
"$changed" { FL; return yD_CHANGED; }
"$countbits" { FL; return yD_COUNTBITS; }
"$countones" { FL; return yD_COUNTONES; }
"$dimensions" { FL; return yD_DIMENSIONS; }

3
src/verilog.y
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@ -690,6 +690,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yD_C "$c"
%token<fl> yD_CAST "$cast"
%token<fl> yD_CEIL "$ceil"
%token<fl> yD_CHANGED "$changed"
%token<fl> yD_CLOG2 "$clog2"
%token<fl> yD_COS "$cos"
%token<fl> yD_COSH "$cosh"
@ -3619,6 +3620,8 @@ system_f_call_or_t<nodep>: // IEEE: part of system_tf_call (can be task or func)
| yD_BITSTOSHORTREAL '(' expr ')' { $$ = new AstBitsToRealD($1,$3); UNSUPREAL($1); }
| yD_CAST '(' expr ',' expr ')' { $$ = new AstCastDynamic($1, $3, $5); }
| yD_CEIL '(' expr ')' { $$ = new AstCeilD($1,$3); }
| yD_CHANGED '(' expr ')' { $$ = new AstLogNot($1, new AstStable($1, $3)); }
| yD_CHANGED '(' expr ',' expr ')' { $$ = $3; BBUNSUP($1, "Unsupported: $changed and clock arguments"); }
| yD_CLOG2 '(' expr ')' { $$ = new AstCLog2($1,$3); }
| yD_COS '(' expr ')' { $$ = new AstCosD($1,$3); }
| yD_COSH '(' expr ')' { $$ = new AstCoshD($1,$3); }

0
test_regress/t/t_fell.pl Normal file → Executable file
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17
test_regress/t/t_past_unsup_bad.out
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@ -1,4 +1,19 @@
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments
13 | if ($past(d, 0, 0, 0)) $stop;
13 | if ($past(d, 0, 0)) $stop;
| ^~~~~
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:14:11: Unsupported: $past expr2 and clock arguments
14 | if ($past(d, 0, 0, clk)) $stop;
| ^~~~~
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:15:11: Unsupported: $fell and clock arguments
15 | if ($fell(d, clk)) $stop;
| ^~~~~
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:16:11: Unsupported: $rose and clock arguments
16 | if ($rose(d, clk)) $stop;
| ^~~~~
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:17:11: Unsupported: $stable and clock arguments
17 | if ($stable(d, clk)) $stop;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_past_unsup_bad.v:18:11: Unsupported: $changed and clock arguments
18 | if ($changed(d, clk)) $stop;
| ^~~~~~~~
%Error: Exiting due to

7
test_regress/t/t_past_unsup_bad.v
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@ -10,6 +10,11 @@ module t (d, clk);
always @ (posedge clk) begin
// Unsupported
if ($past(d, 0, 0, 0)) $stop;
if ($past(d, 0, 0)) $stop;
if ($past(d, 0, 0, clk)) $stop;
if ($fell(d, clk)) $stop;
if ($rose(d, clk)) $stop;
if ($stable(d, clk)) $stop;
if ($changed(d, clk)) $stop;
end
endmodule

0
test_regress/t/t_rose.pl Normal file → Executable file
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0
test_regress/t/t_stable.pl Normal file → Executable file
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4
test_regress/t/t_stable.v
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@ -56,9 +56,11 @@ module Test (/*AUTOARG*/
// In clock expression
$write("dly0=%0d, in=%0d, stable=%0d, past=%0d\n", dly0, in, $stable(dly0), $past(dly0));
if ($stable(dly0)) $stop;
if (!$changed(dly0)) $stop;
end
assert property (@(posedge clk) !$stable(dly0));
assert property (@(posedge clk) $changed(dly0));
endmodule
module Test2 (/*AUTOARG*/
@ -74,8 +76,10 @@ module Test2 (/*AUTOARG*/
always @(posedge clk) begin
dly0 <= in;
if (!$stable(dly0[31:4])) $stop;
if ($changed(dly0[31:4])) $stop;
end
default clocking @(posedge clk); endclocking
assert property ($stable(dly0[31:4]));
assert property (!$changed(dly0[31:4]));
endmodule