From 1dce6b2500760428a56b59a7b00b3256f1faf5aa Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 23 Aug 2020 11:34:19 -0400 Subject: [PATCH] Support $stable --- src/verilog.l | 1 + src/verilog.y | 3 +++ test_regress/t/t_fell.pl | 0 test_regress/t/t_past_unsup_bad.out | 17 ++++++++++++++++- test_regress/t/t_past_unsup_bad.v | 7 ++++++- test_regress/t/t_rose.pl | 0 test_regress/t/t_stable.pl | 0 test_regress/t/t_stable.v | 4 ++++ 8 files changed, 30 insertions(+), 2 deletions(-) mode change 100644 => 100755 test_regress/t/t_fell.pl mode change 100644 => 100755 test_regress/t/t_rose.pl mode change 100644 => 100755 test_regress/t/t_stable.pl diff --git a/src/verilog.l b/src/verilog.l index 30020dd94..4394b2650 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -420,6 +420,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} { /* System Tasks */ "$bits" { FL; return yD_BITS; } + "$changed" { FL; return yD_CHANGED; } "$countbits" { FL; return yD_COUNTBITS; } "$countones" { FL; return yD_COUNTONES; } "$dimensions" { FL; return yD_DIMENSIONS; } diff --git a/src/verilog.y b/src/verilog.y index 50ba6ebdb..55cbb221a 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -690,6 +690,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yD_C "$c" %token yD_CAST "$cast" %token yD_CEIL "$ceil" +%token yD_CHANGED "$changed" %token yD_CLOG2 "$clog2" %token yD_COS "$cos" %token yD_COSH "$cosh" @@ -3619,6 +3620,8 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task or func) | yD_BITSTOSHORTREAL '(' expr ')' { $$ = new AstBitsToRealD($1,$3); UNSUPREAL($1); } | yD_CAST '(' expr ',' expr ')' { $$ = new AstCastDynamic($1, $3, $5); } | yD_CEIL '(' expr ')' { $$ = new AstCeilD($1,$3); } + | yD_CHANGED '(' expr ')' { $$ = new AstLogNot($1, new AstStable($1, $3)); } + | yD_CHANGED '(' expr ',' expr ')' { $$ = $3; BBUNSUP($1, "Unsupported: $changed and clock arguments"); } | yD_CLOG2 '(' expr ')' { $$ = new AstCLog2($1,$3); } | yD_COS '(' expr ')' { $$ = new AstCosD($1,$3); } | yD_COSH '(' expr ')' { $$ = new AstCoshD($1,$3); } diff --git a/test_regress/t/t_fell.pl b/test_regress/t/t_fell.pl old mode 100644 new mode 100755 diff --git a/test_regress/t/t_past_unsup_bad.out b/test_regress/t/t_past_unsup_bad.out index 6d635d12b..9f8b2bb83 100644 --- a/test_regress/t/t_past_unsup_bad.out +++ b/test_regress/t/t_past_unsup_bad.out @@ -1,4 +1,19 @@ %Error-UNSUPPORTED: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments - 13 | if ($past(d, 0, 0, 0)) $stop; + 13 | if ($past(d, 0, 0)) $stop; | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup_bad.v:14:11: Unsupported: $past expr2 and clock arguments + 14 | if ($past(d, 0, 0, clk)) $stop; + | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup_bad.v:15:11: Unsupported: $fell and clock arguments + 15 | if ($fell(d, clk)) $stop; + | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup_bad.v:16:11: Unsupported: $rose and clock arguments + 16 | if ($rose(d, clk)) $stop; + | ^~~~~ +%Error-UNSUPPORTED: t/t_past_unsup_bad.v:17:11: Unsupported: $stable and clock arguments + 17 | if ($stable(d, clk)) $stop; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_past_unsup_bad.v:18:11: Unsupported: $changed and clock arguments + 18 | if ($changed(d, clk)) $stop; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup_bad.v b/test_regress/t/t_past_unsup_bad.v index 750897cb2..edcc5c490 100644 --- a/test_regress/t/t_past_unsup_bad.v +++ b/test_regress/t/t_past_unsup_bad.v @@ -10,6 +10,11 @@ module t (d, clk); always @ (posedge clk) begin // Unsupported - if ($past(d, 0, 0, 0)) $stop; + if ($past(d, 0, 0)) $stop; + if ($past(d, 0, 0, clk)) $stop; + if ($fell(d, clk)) $stop; + if ($rose(d, clk)) $stop; + if ($stable(d, clk)) $stop; + if ($changed(d, clk)) $stop; end endmodule diff --git a/test_regress/t/t_rose.pl b/test_regress/t/t_rose.pl old mode 100644 new mode 100755 diff --git a/test_regress/t/t_stable.pl b/test_regress/t/t_stable.pl old mode 100644 new mode 100755 diff --git a/test_regress/t/t_stable.v b/test_regress/t/t_stable.v index 9b9a831b7..114a10f89 100644 --- a/test_regress/t/t_stable.v +++ b/test_regress/t/t_stable.v @@ -56,9 +56,11 @@ module Test (/*AUTOARG*/ // In clock expression $write("dly0=%0d, in=%0d, stable=%0d, past=%0d\n", dly0, in, $stable(dly0), $past(dly0)); if ($stable(dly0)) $stop; + if (!$changed(dly0)) $stop; end assert property (@(posedge clk) !$stable(dly0)); + assert property (@(posedge clk) $changed(dly0)); endmodule module Test2 (/*AUTOARG*/ @@ -74,8 +76,10 @@ module Test2 (/*AUTOARG*/ always @(posedge clk) begin dly0 <= in; if (!$stable(dly0[31:4])) $stop; + if ($changed(dly0[31:4])) $stop; end default clocking @(posedge clk); endclocking assert property ($stable(dly0[31:4])); + assert property (!$changed(dly0[31:4])); endmodule