forked from github/verilator
Fix crash when formatting constant wider than 1023 bits (#2260)
This commit is contained in:
parent
5c966ec510
commit
08b74e5ab9
@ -583,9 +583,12 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
|
||||
case 'd': { // Unsigned decimal
|
||||
bool issigned = (code == '~');
|
||||
if (fmtsize == "") {
|
||||
double mantissabits = this->width() - (issigned?1:0);
|
||||
double maxval = pow(2.0, mantissabits);
|
||||
double dchars = log10(maxval)+1.0;
|
||||
const double mantissabits = this->width() - (issigned ? 1 : 0);
|
||||
// To get the number of digits required, we want to compute
|
||||
// log10(2**mantissabits) and round it up. To be able to handle
|
||||
// a very wide mantissa, we use log2(2**mantissabits)/log2(10),
|
||||
// which is simply (+1.0 is for rounding bias):
|
||||
double dchars = mantissabits / 3.321928094887362 + 1.0;
|
||||
if (issigned) dchars++; // space for sign
|
||||
fmtsize = cvtToStr(int(dchars));
|
||||
}
|
||||
|
2
test_regress/t/t_format_wide_decimal.out
Normal file
2
test_regress/t/t_format_wide_decimal.out
Normal file
@ -0,0 +1,2 @@
|
||||
179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137215
|
||||
*-* All Finished *-*
|
24
test_regress/t/t_format_wide_decimal.pl
Executable file
24
test_regress/t/t_format_wide_decimal.pl
Executable file
@ -0,0 +1,24 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2020 by Geza Lore. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ["-Wall"]
|
||||
);
|
||||
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
expect_filename => $Self->{golden_filename},
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
20
test_regress/t/t_format_wide_decimal.v
Normal file
20
test_regress/t/t_format_wide_decimal.v
Normal file
@ -0,0 +1,20 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// Copyright 2020 by Geza Lore. This program is free software; you can
|
||||
// redistribute it and/or modify it under the terms of either the GNU
|
||||
// Lesser General Public License Version 3 or the Perl Artistic License
|
||||
// Version 2.0.
|
||||
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
module t_format_wide_decimal;
|
||||
|
||||
initial begin
|
||||
// Format very wide constant number (which has more bits than can
|
||||
// be counted in exponent of a double precision float), with %d.
|
||||
$display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff);
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
Loading…
Reference in New Issue
Block a user