diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 72d6a61e6..b9172f90e 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -583,9 +583,12 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const {
     case 'd': {  // Unsigned decimal
         bool issigned = (code == '~');
         if (fmtsize == "") {
-            double mantissabits = this->width() - (issigned?1:0);
-            double maxval = pow(2.0, mantissabits);
-            double dchars = log10(maxval)+1.0;
+            const double mantissabits = this->width() - (issigned ? 1 : 0);
+            // To get the number of digits required, we want to compute
+            // log10(2**mantissabits) and round it up. To be able to handle
+            // a very wide mantissa, we use log2(2**mantissabits)/log2(10),
+            // which is simply (+1.0 is for rounding bias):
+            double dchars = mantissabits / 3.321928094887362 + 1.0;
             if (issigned) dchars++;  // space for sign
             fmtsize = cvtToStr(int(dchars));
         }
diff --git a/test_regress/t/t_format_wide_decimal.out b/test_regress/t/t_format_wide_decimal.out
new file mode 100644
index 000000000..4c5c7138a
--- /dev/null
+++ b/test_regress/t/t_format_wide_decimal.out
@@ -0,0 +1,2 @@
+179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137215
+*-* All Finished *-*
diff --git a/test_regress/t/t_format_wide_decimal.pl b/test_regress/t/t_format_wide_decimal.pl
new file mode 100755
index 000000000..81690404c
--- /dev/null
+++ b/test_regress/t/t_format_wide_decimal.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Geza Lore. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["-Wall"]
+    );
+
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_format_wide_decimal.v b/test_regress/t/t_format_wide_decimal.v
new file mode 100644
index 000000000..c901f959d
--- /dev/null
+++ b/test_regress/t/t_format_wide_decimal.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Copyright 2020 by Geza Lore. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module t_format_wide_decimal;
+
+   initial begin
+      // Format very wide constant number (which has more bits than can
+      // be counted in exponent of a double precision float), with %d.
+      $display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule