forked from github/verilator
39 lines
827 B
Systemverilog
39 lines
827 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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out, out2,
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// Inputs
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clk, a0, d0, d1
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);
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input clk;
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input [1:0] a0;
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input [7:0] d0;
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input [7:0] d1;
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output reg [31:0] out;
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output reg [15:0] out2;
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reg [7:0] mem [4];
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always @(posedge clk) begin
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mem[a0] <= d0; // <--- Warning
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end
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always @(negedge clk) begin
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mem[a0] <= d1; // <--- Warning
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end
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assign out = {mem[3],mem[2],mem[1],mem[0]};
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always @(posedge clk) begin
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out2[7:0] <= d0; // <--- Warning
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end
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always @(negedge clk) begin
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out2[15:8] <= d0; // <--- Warning
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end
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endmodule
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