Fix --waiver-output for multiline warnings (#2429) (#3141)

docs/CONTRIBUTORS

@@ -48,6 +48,7 @@ Josh Redford
 Julien Margetts
 Kaleb Barrett
 Kanad Kanhere
+Keith Colbert
 Kevin Kiningham
 Krzysztof Bieganski
 Kuba Ober

src/V3Waiver.cpp

@@ -24,8 +24,11 @@
 void V3Waiver::addEntry(V3ErrorCode errorCode, const std::string& filename,
                         const std::string& str) {
     std::stringstream entry;
+    const size_t pos = str.find('\n');
     entry << "lint_off -rule " << errorCode.ascii() << " -file \"*" << filename << "\" -match \""
-          << str << "\"";
+          << str.substr(0, pos);
+    if (pos != std::string::npos) entry << "*";
+    entry << "\"";
     s_waiverList.push_back(entry.str());
 }
 

test_regress/t/t_multiline_waivers.pl

@@ -0,0 +1,29 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+my $out_filename = "$Self->{obj_dir}/$Self->{name}_waiver_gen.vlt";
+my $waiver_filename = "$Self->{obj_dir}/$Self->{name}_waiver.vlt";
+
+compile(
+    v_flags2 => ['--waiver-output', $out_filename],
+    fails => 1,
+    );
+
+file_sed($out_filename, $waiver_filename,
+         sub { s/\/\/ lint_off/lint_off/g; });
+
+compile(
+    v_flags2 => [$waiver_filename],
+    );
+
+ok(1);
+1;

test_regress/t/t_multiline_waivers.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Outputs
+   out, out2,
+   // Inputs
+   clk, a0, d0, d1
+   );
+
+   input clk;
+   input [1:0] a0;
+   input [7:0] d0;
+   input [7:0] d1;
+   output reg [31:0] out;
+   output reg [15:0] out2;
+
+   reg [7:0]         mem [4];
+
+   always @(posedge clk) begin
+      mem[a0] <= d0;  // <--- Warning
+   end
+   always @(negedge clk) begin
+      mem[a0] <= d1;  // <--- Warning
+   end
+   assign out = {mem[3],mem[2],mem[1],mem[0]};
+
+   always @(posedge clk) begin
+      out2[7:0] <= d0;  // <--- Warning
+   end
+   always @(negedge clk) begin
+      out2[15:8] <= d0;  // <--- Warning
+   end
+
+endmodule