forked from github/verilator
26 lines
617 B
Systemverilog
26 lines
617 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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interface sv_if();
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logic a /*verilator public_flat_rw*/;
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endinterface
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module top ();
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sv_if sv_if_i();
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// Workaround for bug3937:
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// logic d /*verilator public_flat_rw*/;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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