forked from github/verilator
Fix VPI upper interface scopes not found (#3937).
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@ -25,6 +25,7 @@ Verilator 5.007 devel
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* Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal]
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* Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk]
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* Fix very long VPI signal names (#3929). [Marlon James]
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* Fix VPI upper interface scopes not found (#3937). [David Stanford]
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Verilator 5.006 2023-01-22
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@ -186,7 +186,7 @@ class EmitCSyms final : EmitCBaseVisitor {
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void varHierarchyScopes(string scp) {
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while (!scp.empty()) {
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const auto scpit = m_vpiScopeCandidates.find(scp);
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const auto scpit = m_vpiScopeCandidates.find(scopeSymString(scp));
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if ((scpit != m_vpiScopeCandidates.end())
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&& (m_scopeNames.find(scp) == m_scopeNames.end())) {
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const auto scopeNameit = m_scopeNames.find(scpit->second.m_symName);
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@ -314,8 +314,9 @@ class EmitCSyms final : EmitCBaseVisitor {
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const string name = nodep->scopep()->shortName() + "__DOT__" + nodep->name();
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const string name_pretty = AstNode::vpiName(name);
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const int timeunit = m_modp->timeunit().powerOfTen();
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m_vpiScopeCandidates.insert(std::make_pair(
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name, ScopeData{scopeSymString(name), name_pretty, timeunit, type}));
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m_vpiScopeCandidates.insert(
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std::make_pair(scopeSymString(name),
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ScopeData{scopeSymString(name), name_pretty, timeunit, type}));
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}
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}
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void visit(AstScope* nodep) override {
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@ -328,15 +329,15 @@ class EmitCSyms final : EmitCBaseVisitor {
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const string type = VN_IS(nodep->modp(), Package) ? "SCOPE_OTHER" : "SCOPE_MODULE";
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const string name_pretty = AstNode::vpiName(nodep->shortName());
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const int timeunit = m_modp->timeunit().powerOfTen();
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m_vpiScopeCandidates.insert(
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std::make_pair(nodep->name(), ScopeData{scopeSymString(nodep->name()), name_pretty,
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timeunit, type}));
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m_vpiScopeCandidates.insert(std::make_pair(
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scopeSymString(nodep->name()),
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ScopeData{scopeSymString(nodep->name()), name_pretty, timeunit, type}));
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}
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}
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void visit(AstScopeName* nodep) override {
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const string name = nodep->scopeSymName();
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// UINFO(9,"scnameins sp "<<nodep->name()<<" sp "<<nodep->scopePrettySymName()
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// <<" ss"<<name<<endl);
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// UINFO(9, "scnameins sp " << nodep->name() << " sp " << nodep->scopePrettySymName()
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// << " ss" << name << endl);
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const int timeunit = m_modp ? m_modp->timeunit().powerOfTen() : 0;
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m_scopeNames.emplace(
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name, ScopeData{name, nodep->scopePrettySymName(), timeunit, "SCOPE_OTHER"});
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123
test_regress/t/t_vpi_module_empty.cpp
Normal file
123
test_regress/t/t_vpi_module_empty.cpp
Normal file
@ -0,0 +1,123 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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//
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// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#ifdef IS_VPI
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#include "vpi_user.h"
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#include <cstdlib>
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#else
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "verilated_vpi.h"
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#include "Vt_vpi_module_empty.h"
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#include "Vt_vpi_module_empty__Dpi.h"
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#include "svdpi.h"
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#endif
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#include <cstdio>
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#include <cstring>
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#include <iostream>
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// These require the above. Comment prevents clang-format moving them
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#include "TestSimulator.h"
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#include "TestVpi.h"
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// __FILE__ is too long
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#define FILENM "t_vpi_module_empty.cpp"
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#define DEBUG \
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if (0) printf
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#define CHECK_RESULT_NZ(got) \
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if (!(got)) { \
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printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \
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return __LINE__; \
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}
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extern "C" {
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int mon_check() {
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#ifdef TEST_VERBOSE
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printf("-mon_check()\n");
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#endif
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TestVpiHandle it = vpi_iterate(vpiModule, NULL);
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CHECK_RESULT_NZ(it);
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return 0; // Ok
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}
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}
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//======================================================================
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#ifdef IS_VPI
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static int mon_check_vpi() {
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TestVpiHandle href = vpi_handle(vpiSysTfCall, 0);
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s_vpi_value vpi_value;
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vpi_value.format = vpiIntVal;
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vpi_value.value.integer = mon_check();
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vpi_put_value(href, &vpi_value, NULL, vpiNoDelay);
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return 0;
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}
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static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check",
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(PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0},
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0};
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// cver entry
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void vpi_compat_bootstrap(void) {
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p_vpi_systf_data systf_data_p;
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systf_data_p = &(vpi_systf_data[0]);
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while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++);
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}
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// icarus entry
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void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
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#else
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int main(int argc, char** argv) {
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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uint64_t sim_time = 1100;
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contextp->debug(0);
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contextp->commandArgs(argc, argv);
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// we're going to be checking for these errors do don't crash out
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contextp->fatalOnVpiError(0);
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// Test second construction
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const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
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// Note null name - we're flattening it out
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""}};
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#ifdef VERILATOR
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#ifdef TEST_VERBOSE
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contextp->scopesDump();
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#endif
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#endif
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topp->eval();
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VerilatedVpi::callValueCbs();
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TestVpiHandle vh = vpi_handle_by_name((PLI_BYTE8*)"top.sv_if_i.a", NULL);
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CHECK_RESULT_NZ(vh);
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TestVpiHandle it = vpi_iterate(vpiModule, NULL);
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CHECK_RESULT_NZ(it);
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topp->final();
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return 0;
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}
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#endif
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30
test_regress/t/t_vpi_module_empty.pl
Executable file
30
test_regress/t/t_vpi_module_empty.pl
Executable file
@ -0,0 +1,30 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2010 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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skip("Known compiler limitation")
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if $Self->cxx_version =~ /\(GCC\) 4.4/;
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compile(
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make_top_shell => 0,
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make_main => 0,
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make_pli => 1,
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iv_flags2 => ["-g2005-sv"],
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verilator_flags2 => ["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name $Self->{t_dir}/t_vpi_module_empty.cpp"],
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);
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execute(
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use_libvpi => 1,
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check_finished => 1
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);
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ok(1);
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1;
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25
test_regress/t/t_vpi_module_empty.v
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25
test_regress/t/t_vpi_module_empty.v
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@ -0,0 +1,25 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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interface sv_if();
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logic a /*verilator public_flat_rw*/;
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endinterface
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module top ();
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sv_if sv_if_i();
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// Workaround for bug3937:
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// logic d /*verilator public_flat_rw*/;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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