verilator/test_regress/t/t_trace_two_hdrfst_cc.out

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$date
Wed Feb 23 00:03:39 2022
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$end
$version
fstWriter
$end
$timescale
1ps
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$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc [31:0] $end
$var integer 32 # c_trace_on [31:0] $end
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$scope module sub $end
$var integer 32 $ inside_sub_a [31:0] $end
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$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
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$var wire 1 % clk $end
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$scope module t $end
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$var wire 1 % clk $end
$var integer 32 & cyc [31:0] $end
$var integer 32 ' c_trace_on [31:0] $end
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$var real 64 ( r $end
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$scope module sub $end
$var integer 32 ) inside_sub_a [31:0] $end
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$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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$dumpvars
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b00000000000000000000000000000010 )
r0 (
b00000000000000000000000000000000 '
b00000000000000000000000000000001 &
0%
b00000000000000000000000000000001 $
b00000000000000000000000000000000 #
b00000000000000000000000000000001 "
0!
$end
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#10
1!
b00000000000000000000000000000010 "
b00000000000000000000000000000011 #
1%
r0.1 (
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#15
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0%
0!
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#20
1!
1%
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r0.2 (
b00000000000000000000000000000100 #
b00000000000000000000000000000011 "
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#25
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0%
0!
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#30
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1%
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b00000000000000000000000000000100 "
b00000000000000000000000000000101 #
r0.3 (
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#35
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0%
0!
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#40
1!
1%
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r0.4 (
b00000000000000000000000000000110 #
b00000000000000000000000000000101 "
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#45
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0%
0!
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#50
1!
1%
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b00000000000000000000000000000110 "
b00000000000000000000000000000111 #
r0.5 (
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#55
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0%
0!
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#60
1!
1%
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r0.6 (
b00000000000000000000000000001000 #
b00000000000000000000000000000111 "
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#65
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0%
0!
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#70
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1%
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b00000000000000000000000000001000 "
b00000000000000000000000000001001 #
r0.7 (
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#75
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0!
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#80
1!
1%
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r0.7999999999999999 (
b00000000000000000000000000001010 #
b00000000000000000000000000001001 "
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#85
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0%
0!
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#90
1!
1%
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b00000000000000000000000000001010 "
b00000000000000000000000000001011 #
r0.8999999999999999 (
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#95
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0%
0!
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#100
1!
1%
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r0.9999999999999999 (
b00000000000000000000000000001100 #
b00000000000000000000000000001011 "