verilator/test_regress/t/t_trace_two_hdrfst_cc.out

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$date
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Sat Mar 7 18:27:58 2020
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$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module topa $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc $end
$var integer 32 # c_trace_on $end
$scope module sub $end
$var integer 32 $ inside_sub_a $end
$upscope $end
$upscope $end
$upscope $end
$scope module topb $end
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$var wire 1 % clk $end
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$scope module t $end
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$var wire 1 % clk $end
$var integer 32 & cyc $end
$var integer 32 ' c_trace_on $end
$var real 64 ( r $end
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$scope module sub $end
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$var integer 32 ) inside_sub_a $end
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$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
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b00000000000000000000000000000001 "
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b00000000000000000000000000000000 #
b00000000000000000000000000000001 $
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b00000000000000000000000000000000 '
r0 (
b00000000000000000000000000000010 )
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#10
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r0.1 (
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