forked from github/verilator
29 lines
605 B
Systemverilog
29 lines
605 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg a;
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reg b;
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initial begin
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#10;
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expect (@(posedge clk) a ##1 b) a = 110;
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#10;
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expect (@(posedge clk) a ##1 b) else a = 299;
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#10;
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expect (@(posedge clk) a ##1 b) a = 300; else a = 399;
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end
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// TODO set a/b appropriately - this is just a parsing test currently
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endmodule
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