forked from github/verilator
32 lines
712 B
Systemverilog
32 lines
712 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef verilator
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`define stop $stop
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`else
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`define stop
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`endif
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Cls;
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bit b;
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int i;
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bit [15:0] carray4 [4];
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.b = '1;
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c.i = 42;
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$display("'%p'", c);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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