forked from github/verilator
36 lines
1.0 KiB
Systemverilog
36 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sub sub();
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endmodule
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module sub;
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// no_inline_module, so it goes into separate file
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/* verilator no_inline_module */
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// Goes into const pool which is separate file
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wire bit [255:0] C = {32'h1111_1111,
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32'h2222_2222,
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32'h3333_3333,
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32'h4444_4444,
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32'h5555_5555,
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32'h6666_6666,
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32'h7777_7777,
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32'h8888_8888};
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initial begin
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// Note: Base index via $c to prevent optimization
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$display("0x%32x", C[$c(0*32)+:32]);
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$display("0x%32x", C[$c(2*32)+:32]);
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$display("0x%32x", C[$c(4*32)+:32]);
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$display("0x%32x", C[$c(6*32)+:32]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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