verilator/test_regress/t/t_fuzz_negwidth_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

int a = -12'd1;
int b = 65536'd1;
int c = 1231232312312312'd1;
Fix misc bad-syntax crashes, bug1530. 2019-09-30 23:48:01 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2019 by Wilson Snyder.`
			`// SPDX-License-Identifier: CC0-1.0`
Fix misc bad-syntax crashes, bug1530. 2019-09-30 23:48:01 +00:00
			`int a = -12'd1;`
Set maximum number width (#2128) Adjust the maximum number width to 64K. Add --max-num-width option to adjust this setting. Closes #2082 2020-01-21 11:17:31 +00:00			`int b = 65536'd1;`
			`int c = 1231232312312312'd1;`