forked from github/verilator
18 lines
498 B
Coq
18 lines
498 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t;
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export "DPI-C" task dpix_twice;
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export "DPI-C" dpix_t_int_renamed = task dpix_twice;
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task dpix_twice(input int i, output int o); o = ~i; endtask
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initial begin
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$stop;
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end
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endmodule
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