verilator/test_regress/t/t_delay_stmtdly_bad.out

%Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring timing control on this assignment.
                                     : ... In instance t
   22 |    assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
      |             ^~~~~~~~~~~~~~~~~~
                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring timing control on this assignment.
                                     : ... In instance t
   27 |          dly0 <= #0 32'h11;
      |                   ^
%Warning-ASSIGNDLY: t/t_delay.v:30:19: Unsupported: Ignoring timing control on this assignment.
                                     : ... In instance t
   30 |          dly0 <= #0.12 dly0 + 32'h12;
      |                   ^~~~
%Warning-ASSIGNDLY: t/t_delay.v:38:26: Unsupported: Ignoring timing control on this assignment.
                                     : ... In instance t
   38 |          dly0 <= #(dly_s.dly) 32'h55;
      |                          ^~~
%Warning-STMTDLY: t/t_delay.v:43:11: Unsupported: Ignoring delay on this delayed statement.
                                   : ... In instance t
   43 |          #100 $finish;
      |           ^~~
%Warning-UNUSED: t/t_delay.v:20:12: Signal is not used: 'dly_s'
                                  : ... In instance t
   20 |    dly_s_t dly_s;
      |            ^~~~~
%Warning-BLKSEQ: t/t_delay.v:37:20: Blocking assignment '=' in sequential logic process
                                  : ... Suggest using delayed assignment '<='
   37 |          dly_s.dly = 55;
      |                    ^
%Error: Exiting due to