forked from github/verilator
46 lines
1.1 KiB
Systemverilog
46 lines
1.1 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Cls;
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integer imembera;
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integer imemberb;
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endclass : Cls
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module t (/*AUTOARG*/);
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initial begin
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string a [*];
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string k;
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string v;
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Cls x;
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v = a.num("badarg");
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v = a.size("badarg");
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v = a.exists(); // Bad
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v = a.exists(k, "bad2");
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a.delete(k, "bad2");
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a.sort; // Not legal on assoc
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a.rsort; // Not legal on assoc
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a.reverse; // Not legal on assoc
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a.shuffle; // Not legal on assoc
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a.first; // Not legal on wildcard
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a.last; // Not legal on wildcard
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a.next; // Not legal on wildcard
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a.prev; // Not legal on wildcard
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a.unique_index; // Not legal on wildcard
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a.find_index; // Not legal on wildcard
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a.find_first_index; // Not legal on wildcard
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a.find_last_index; // Not legal on wildcard
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a[x] = "bad";
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end
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endmodule
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