forked from github/verilator
43 lines
726 B
Plaintext
43 lines
726 B
Plaintext
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$date
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Tue Aug 28 16:59:34 2018
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$end
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$version
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lxt2vcd
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 ! clk $end
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$scope module t $end
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$var wire 32 " cnt [31:0] $end
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$var wire 96 # v(0) [95:0] $end
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$var wire 96 $ v(1) [95:0] $end
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$var wire 96 % v(2) [95:0] $end
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$var wire 1 ! clk $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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#0
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0!
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b0 "
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b1100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
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b1000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
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b100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
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#10
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b1 "
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1!
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#15
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0!
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#20
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1!
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b10 "
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#25
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0!
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#30
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1!
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b11 "
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#35
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0!
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#40
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1!
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