$date
	Tue Aug 28 16:59:34 2018
$end
$version
	lxt2vcd
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 32 " cnt [31:0] $end
$var wire 96 # v(0) [95:0] $end
$var wire 96 $ v(1) [95:0] $end
$var wire 96 % v(2) [95:0] $end
$var wire 1 ! clk $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
#0
0!
b0 "
b1100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
b1000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
b100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
#10
b1 "
1!
#15
0!
#20
1!
b10 "
#25
0!
#30
1!
b11 "
#35
0!
#40
1!