forked from github/verilator
22 lines
413 B
Systemverilog
22 lines
413 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Alex Solomatnikov
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module t;
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sub #(.REAL(2.0)) sub;
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endmodule
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module sub ();
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timeunit 1ns;
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timeprecision 1ps;
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parameter REAL = 0.0;
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initial begin
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$display("REAL %g", REAL);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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