Fix compile error on public real parameters by suppressing, bug1261.

This commit is contained in:
Wilson Snyder 2018-01-16 19:53:50 -05:00
parent 7ee6efab74
commit bd1f1e8699
4 changed files with 44 additions and 0 deletions

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@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 3.919 devel
**** Fix compile error on public real parameters by suppressing, bug1261. [Alex Solomatnikov]
* Verilator 3.918 2018-01-02

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@ -2040,6 +2040,8 @@ void EmitCImp::emitInt(AstNodeModule* modp) {
putsDecoration("// enum WData "+varp->name()+" //wide");
} else if (!varp->valuep()->castConst()) { // Unsupported for output
//putsDecoration("// enum ..... "+varp->name()+" //not simple value, see variable above instead");
} else if (varp->dtypep()->castBasicDType()
&& varp->dtypep()->castBasicDType()->isOpaque()) { // Can't put out e.g. doubles
} else {
puts("enum ");
puts(varp->isQuad()?"_QData":"_IData");

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@ -0,0 +1,19 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
verilator_flags2 => ['--cc --public'],
);
execute (
check_finished=>1,
);
ok(1);
1;

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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Alex Solomatnikov
module t;
sub #(.REAL(2.0)) sub;
endmodule
module sub ();
timeunit 1ns;
timeprecision 1ps;
parameter REAL = 0.0;
initial begin
$display("REAL %g", REAL);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule