forked from github/verilator
28 lines
519 B
Systemverilog
28 lines
519 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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ov,
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// Inputs
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clk, iv
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);
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parameter N = 4;
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input clk;
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input [63:0] iv[N-1:0];
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output logic [63:0] ov[N-1:0];
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genvar i;
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generate
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always @(posedge clk) begin
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for (i=0; i<N; i=i+1) begin
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ov[i] <= iv[i];
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end
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end
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endgenerate
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endmodule
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