Add warning on genvar in normal for loop, #2143.

Changes

@@ -31,6 +31,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add parameter to set maximum signal width, #2082. [Øyvind Harboe]
 
+****  Add warning on genvar in normal for loop, #2143. [yurivict]
+
 ****  Fix VPI scope naming for public modules. [Nandu Raj]
 
 ****  Fix FST tracing of enums inside structs. [fsiegle]

src/V3Unroll.cpp

@@ -124,6 +124,12 @@ private:
         if (VN_IS(nodep, GenFor) && !m_forVarp->isGenVar()) {
             nodep->v3error("Non-genvar used in generate for: "<<m_forVarp->prettyNameQ()<<endl);
         }
+        else if (!VN_IS(nodep, GenFor) && m_forVarp->isGenVar()) {
+            nodep->v3error("Genvar not legal in non-generate for (IEEE 2017 27.4): "
+                           << m_forVarp->prettyNameQ() << endl
+                           << nodep->warnMore()
+                           << "... Suggest move for loop upwards to generate-level scope.");
+        }
         if (m_generate) V3Const::constifyParamsEdit(initAssp->rhsp());  // rhsp may change
 
         // This check shouldn't be needed when using V3Simulate

test_regress/t/t_genvar_for_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_genvar_for_bad.v:22: Genvar not legal in non-generate for (IEEE 2017 27.4): 't.i'
+                               : ... Suggest move for loop upwards to generate-level scope.
+         for (i=0; i<N; i=i+1) begin
+         ^~~
+%Error: Exiting due to

test_regress/t/t_genvar_for_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_genvar_for_bad.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2020 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   ov,
+   // Inputs
+   clk, iv
+   );
+
+   parameter N = 4;
+
+   input         clk;
+   input [63:0]  iv[N-1:0];
+   output logic [63:0] ov[N-1:0];
+
+   genvar        i;
+   generate
+      always @(posedge clk) begin
+         for (i=0; i<N; i=i+1) begin
+            ov[i] <= iv[i];
+         end
+      end
+   endgenerate
+endmodule