verilator/test_regress/t/t_unopt_combo_bad.out

%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:25: Signal unoptimizable: Circular combinational logic: 't.b'
   23 |    wire [31:0]          b;                       
      |                         ^
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    t/t_unopt_combo.v:23:25:      Example path: t.b
                    t/t_unopt_combo.v:124:4:      Example path: ALWAYS
                    t/t_unopt_combo.v:24:25:      Example path: t.c
                    t/t_unopt_combo.v:81:4:      Example path: ALWAYS
                    t/t_unopt_combo.v:23:25:      Example path: t.b
%Error: Exiting due to
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:25: Signal unoptimizable: Circular combinational logic: 't.b'`
			`23 \| wire [31:0] b;`
Add GCC10-style line number prefix when showing source text for errors. 2020-04-04 00:07:46 +00:00			`\| ^`
Tests: Don't expose version numbers 2021-04-24 14:33:49 +00:00			`... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest`
Error continuation lines no longer have %Error prefix. 2019-05-31 00:30:59 +00:00			`... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.`
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`t/t_unopt_combo.v:23:25: Example path: t.b`
			`t/t_unopt_combo.v:124:4: Example path: ALWAYS`
			`t/t_unopt_combo.v:24:25: Example path: t.c`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`t/t_unopt_combo.v:81:4: Example path: ALWAYS`
			`t/t_unopt_combo.v:23:25: Example path: t.b`
Tests: Favor golden files over long regexps. No functional change. 2018-11-03 18:59:04 +00:00			`%Error: Exiting due to`