2020-03-21 15:24:24 +00:00
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%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
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: ... In instance t
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2020-04-04 00:07:46 +00:00
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10 | wire [3:0] foo = 6'h2e;
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| ^
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2021-04-24 14:33:49 +00:00
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... For warning description see https://verilator.org/warn/WIDTH?v=latest
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2019-05-31 00:30:59 +00:00
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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2019-05-02 22:45:32 +00:00
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%Error: Exiting due to
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