Merge branch 'sscs-ose:main' into main

.vscode/settings.json

@@ -0,0 +1,8 @@
+{
+    "cSpell.words": [
+        "Intermodulation",
+        "Nyquist",
+        "tapeouts",
+        "transimpedance"
+    ]
+}

CALL.md

@@ -1,9 +1,11 @@
 
 ## 2023 SSCS “PICO” Open-Source Chipathon
-### – Submission deadline: May 1, 2023 – 
+### – Submission deadline: May 1, 2023 –
 
-The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 
+The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community.
 
 The goal of this chipathon is to bring together IC design newbies, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the rapidly growing open-source IC design movement. In contrast to previous chipathon editions (which were open-ended), this year’s goal is to create a specific set of building blocks that can be re-used to benefit the community as a whole.
 
 The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/).
+
+<img src="figures/overview.png" width="400"/>

FAQ.md

@@ -1,25 +1,16 @@
 # FAQ
 
 Q: Do I need to be an IEEE SSCS member to participate?  
-A: No, but you are encouraged to join and benefit from our broad range of resources. Please refer to this link.  
+A: No, but you are encouraged to join and benefit from our broad range of resources. Please refer to this [link](https://sscs.ieee.org/membership).  
 
 Q: May I re-use someone else’s open-source design?  
 A: Yes! Please be sure to give credit to the original contributor.  
 
 Q: Does my design need to be open-source?  
-A: Yes. Your design must be posted on a git-compatible repo and be publicly accessible. The project top-level must include a license file for an approved open-source license agreement (we recommend using the Apache-2.0 license). Third-party source code must be identified, and source code must contain proper headers. Refer to the Open MPW Shuttle Program FAQ for further guidance.   
+A: Yes. Your design must be posted on a git-compatible repo and be publicly accessible. The project top-level must include a license file for an approved open-source license agreement (we recommend using the Apache-2.0 license). Third-party source code must be identified, and source code must contain proper headers.   
 
 Q: What is the purpose of the planned online meetups?  
-A: We will use these meetings for project presentations, networking among teams, short lectures on various circuit design topics, tool support as well as any other topic that will help you learn and succeed!  
+A: We will use these meetings for project presentations, networking among teams, short lectures on various circuit design topics, tool support as well as any other topic that will help us learn and succeed!  
 
-Q: What happens if I am selected, but cannot finish my design by the chipathon’s tapeout deadline?  
-A: You can participate in a later Google-sponsored Open-MPW run.  
-
-Q: Will I be able to allocate a full 10 mm2 Caravel seat for my tapeout?  
-A: It is possible, but will depend on the size of your block. We will try to combine a number of blocks to maximize chip area utilization and to create useful subsystems (for example, ADC combined with a reference generator). We will use the meetups to plan possible design mergers.  
-
-Q: Will all selected teams be able to tape out?  
-A: We will perform design status audits before the tapeout and may only advance a subset of the designs based on their readiness.  
-
-Q: I am not a participating designer, but would like to contribute as a volunteer/mentor, is this possible?   
+Q: I would like to contribute as a volunteer/mentor, is this possible?   
 A: Yes! Please sign up [here](https://sscs.ieee.org/volunteer-opportunities#SSCD).

README.md

@@ -1,11 +1,11 @@
 # SSCS “PICO” Open-Source Chipathon
 
-<img align="left" width="400" src="overview.png" width="450"/>
+<img align="left" width="400" src="figures/overview.png" width="450"/>
 
 
 
 &nbsp;&nbsp;&nbsp;&nbsp;[Call for proposals](CALL.md)  
-&nbsp;&nbsp;&nbsp;&nbsp;[How to submit a proposal](HOWTO.md)  
+&nbsp;&nbsp;&nbsp;&nbsp;[How to participate](HOWTO.md)  
 &nbsp;&nbsp;&nbsp;&nbsp;[Target specifications](SPECS.md)  
 &nbsp;&nbsp;&nbsp;&nbsp;[Design tools](TOOLS.md)  
 &nbsp;&nbsp;&nbsp;&nbsp;[FAQ](FAQ.md)  

SPECS.md

@@ -1,6 +1,63 @@
+# Target specifications
+
+The purpose of this page is to seed some ideas on what the  “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of a Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage.
+
+<p align="center">
+  <img src="figures/block_diagram.svg" width="650"/>    
+</p>
+
+To our knowledge, there aren't any published prior-art “lab bench on a chip” designs that we can build on. However, we can draw some inspiration from a similar system that was designed for PCB measurements. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal.
+
+Generally, think of this entire project is an experiment. We want to explore what a team of enthusiasts, spread across the globe, can do within the new environment of open-source IC design. Even if we don't succeed at building the complete target system in our first attempt, the community can re-use the various blocks that we design for future iterations or for an entirely different purpose.
+
+What follows below are initial thoughts and baseline specs for each one of our major system components. All teams are encouraged to exceed these requirements and explore what is possible!
+
+**1. Scope MUX and signal conditioning**  
+The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. The Analog Discovery 2 has adjustable offsets in each channel. This may not be needed for our design.
+
+| Specification | Symbol | Baseline requirement | Comment |
+| ------------- | ------ |--------------------- |-------- |
+| Scope input capacitance | Cin | < 5pF | From each diff. input to ground
+| Number of differential input channels   | N  |  $\geq8$  | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks
+| Programmable gain   | G  |  0.25, 0.5, 1, 2, 4, 8 | Gain <1 needed since ADC likely cannot handle rail-to-rail inputs
+| Bandwidth   | BW  |  Maximize | Should be linked to ADC's acquisition bandwidth
+| Noise   | Neq  |  <0.5 LSBrms | Contribution of the front-end to the ADC's sampled noise
 
 
-https://digilent.com/reference/test-and-measurement/analog-discovery-2/start
+**2. AWG MUX and signal conditioning**  
+The arbitrary waveform generator design should have an output MUX that allows the macro's user to direct the DAC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail outputs. The MUX resistance will limit the AWG drive strength, but this should be OK for small on-chip loads. The Analog Discovery 2 has adjustable offsets in each channel. This may not be needed for our design. 
 
-https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide
+| Specification | Symbol | Baseline requirement | Comment |
+| ------------- | ------ |--------------------- |-------- |
+| AWG load capacitance | CL | $\leq$ 10pF | Driver stability must be ensured up to this level
+| Number of differential input channels   | N  |  $\geq8$  | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks
+| Bandwidth   | BW  |  Maximize | Should be linked to DAC's Nyquist bandwidth
+| Slew rate   | SR  |  $\geq V_{peak}\cdot 2\pi BW$ | Align with bandwidth, assuming largest supported signal
+| Output noise | PSD  |  <20nV/rt-Hz | 
 
+**3. Clock generator**  
+The clock generator(s) for both the ADC and DAC should be designed in alignment with the target specs for these converters. For example, the clock generator's jitter should not lead to a significant SNR degradation at the maximum input frequency.
+
+**4. ADCs**  
+The ADC and DAC design tasks will likely the most challenging and time consuming. An important objective is to minimize silicon area while still achieving attractive specs for the given application. Teams working on this block should consider re-using existing designs, as for instance this [12-bit SAR ADC](https://github.com/w32agobot/SKY130_SAR-ADC). It is desirable to have at least two ADCs (as shown in the system diagram) so that two signals can be measured simultaneously in real time, but this is not a must.
+
+| Specification | Symbol | Baseline requirement | Comment |
+| ------------- | ------ |--------------------- |-------- |
+| Sampling rate | fs | $\geq$ 1.5MS/s | 
+| Effective number of bits   | ENOB  |  $\geq9$  | Measured near Nyquist
+| Input capacitance   | Cin  |  $\leq$ 5pF | 
+
+
+**5. DACs**  
+For the DAC, it may be best to aim for a current steering topology (also used in the Analog Discovery 2). Such a DAC will produce a differential output current that is converted to a differential voltage and image-filtered by the AWG signal conditioning block. Off the shelf current steering DACs are typically designed for high currents to interface with 50 Ohm loads. This is not a requirement in our on-chip environment; we can deviate to minimize circuit area. It is desirable to have at least two DACs (as shown in the system diagram) so that two signals can be generated simultaneously in real time, but this is not a must.
+
+| Specification | Symbol | Baseline requirement | Comment |
+| ------------- | ------ |--------------------- |-------- |
+| Update rate | fs | $\geq$ 10MS/s | 
+| Number of bits | B | $\geq$ 10 | 
+| Intermodulation distortion   | IM3  |  $\geq$ -60dB  | Measured near Nyquist
+| Noise spectral density   | NSD  |   |  To be aligned with overall PSD spec for the AWG path
+
+
+**6. Digital interface**  
+One of the primary goals here is to enable a convenient USB interface to a host computer. Teams working on this aspect should design both the on- and off-chip digital circuitry. For the off-chip board, we can consider the lowest cost boards from [Digilent](https://digilent.com/shop/boards-and-components/system-boards/introductory-boards/?sort=priceasc). The USB UART provided [here](https://github.com/ricynlee/cmod-a7-uart-sram-test) could be useful for establishing the communication.

TOOLS.md

@@ -11,7 +11,7 @@ curl -L -o /tmp/silicon-installer.sh https://github.com/proppy/conda-eda/release
 bash /tmp/silicon-installer.sh -p silicon-env -b
 source silicon-env/bin/activate
 ```
- **Note**: Make to check the latest or recommended [conda EDA release](https://github.com/proppy/conda-eda/releases/). Please refer to the [conda EDA documentation](https://hdl.github.io/conda-eda/).
+ **Note**: Be sure to check the latest or recommended [conda EDA release](https://github.com/proppy/conda-eda/releases/). Please refer to the [conda EDA documentation](https://hdl.github.io/conda-eda/).
  
 * A number of useful pointers are also available on the [SSCS OSE Webpage](https://sscs-ose.github.io/)
 * Feel free to post questions to the [#ieee-sscs-dc-23](https://join.slack.com/share/enQtNDc1MjgzMTc4NTYyMC03YTY5NjI0NGUxN2UyMjgzZmI5YTQyYTcxMzQxY2M4NjUyMTk3ODE3ZTgzNTY2ZmQ3M2Y0NjYyZDQ4NWZjYmQ5) Slack channel or open Git Hub issues.

figures/block_diagram.drawio

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