From 7d984d88a0d44a5fc762bbc95a0bbae70a75d700 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 07:22:44 -0800 Subject: [PATCH 01/19] Update TOOLS.md Fixed a typo. --- TOOLS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TOOLS.md b/TOOLS.md index 715ab61..805d8d2 100644 --- a/TOOLS.md +++ b/TOOLS.md @@ -11,7 +11,7 @@ curl -L -o /tmp/silicon-installer.sh https://github.com/proppy/conda-eda/release bash /tmp/silicon-installer.sh -p silicon-env -b source silicon-env/bin/activate ``` - **Note**: Make to check the latest or recommended [conda EDA release](https://github.com/proppy/conda-eda/releases/). Please refer to the [conda EDA documentation](https://hdl.github.io/conda-eda/). + **Note**: Be sure to check the latest or recommended [conda EDA release](https://github.com/proppy/conda-eda/releases/). Please refer to the [conda EDA documentation](https://hdl.github.io/conda-eda/). * A number of useful pointers are also available on the [SSCS OSE Webpage](https://sscs-ose.github.io/) * Feel free to post questions to the [#ieee-sscs-dc-23](https://join.slack.com/share/enQtNDc1MjgzMTc4NTYyMC03YTY5NjI0NGUxN2UyMjgzZmI5YTQyYTcxMzQxY2M4NjUyMTk3ODE3ZTgzNTY2ZmQ3M2Y0NjYyZDQ4NWZjYmQ5) Slack channel or open Git Hub issues. From aaa12b281b37bacc0102d62bf93e44703b954bc3 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:17:29 -0800 Subject: [PATCH 02/19] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f622612..1341e9d 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@     [Call for proposals](CALL.md) -    [How to submit a proposal](HOWTO.md) +    [How to participate](HOWTO.md)     [Target specifications](SPECS.md)     [Design tools](TOOLS.md)     [FAQ](FAQ.md) From 97f6f3f84dac8b931c30187927176af72274ee2c Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:21:08 -0800 Subject: [PATCH 03/19] Update CALL.md --- CALL.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CALL.md b/CALL.md index 384793a..56169d3 100644 --- a/CALL.md +++ b/CALL.md @@ -7,3 +7,5 @@ The IEEE Solid-State Circuits Society is pleased to announce its third open-sour The goal of this chipathon is to bring together IC design newbies, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the rapidly growing open-source IC design movement. In contrast to previous chipathon editions (which were open-ended), this year’s goal is to create a specific set of building blocks that can be re-used to benefit the community as a whole. The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/). + + From b540f585c3c8f68f944e6c4194505a8435d9026e Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:21:34 -0800 Subject: [PATCH 04/19] Update CALL.md --- CALL.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CALL.md b/CALL.md index 56169d3..e15fbb8 100644 --- a/CALL.md +++ b/CALL.md @@ -8,4 +8,4 @@ The goal of this chipathon is to bring together IC design newbies, enthusiasts a The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/). - + From 185598d379358d0161097caa265a0ad41d094d8c Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:21:56 -0800 Subject: [PATCH 05/19] Update CALL.md --- CALL.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CALL.md b/CALL.md index e15fbb8..5e257e2 100644 --- a/CALL.md +++ b/CALL.md @@ -8,4 +8,4 @@ The goal of this chipathon is to bring together IC design newbies, enthusiasts a The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/). - + From e4e92fe05646c3df3cba72466dcc6786d7645939 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:22:11 -0800 Subject: [PATCH 06/19] Update CALL.md --- CALL.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CALL.md b/CALL.md index 5e257e2..f8b84e7 100644 --- a/CALL.md +++ b/CALL.md @@ -8,4 +8,4 @@ The goal of this chipathon is to bring together IC design newbies, enthusiasts a The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/). - + From b277015184fce83e54ab33a1a82cc4b7f60ebadd Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:36:50 -0800 Subject: [PATCH 07/19] Create README.md --- diagrams/README.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 diagrams/README.md diff --git a/diagrams/README.md b/diagrams/README.md new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/diagrams/README.md @@ -0,0 +1 @@ + From 325cb4c8e0f5f668887bf5653c01a08c50542d5a Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:39:04 -0800 Subject: [PATCH 08/19] block diagram.drawio --- diagrams/Untitled Diagram.drawio | 1 + 1 file changed, 1 insertion(+) create mode 100644 diagrams/Untitled Diagram.drawio diff --git a/diagrams/Untitled Diagram.drawio b/diagrams/Untitled Diagram.drawio new file mode 100644 index 0000000..f812011 --- /dev/null +++ b/diagrams/Untitled Diagram.drawio @@ -0,0 +1 @@ +UzV2zq1wL0osyPDNT0nNUTV2VTV2LsrPL4GwciucU3NyVI0MMlNUjV1UjYwMgFjVyA2HrCFY1qAgsSg1rwSLBiADYTaQg2Y1AA== \ No newline at end of file From abfcd5988fa099ec1638c2036a6b8ff234429cd1 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:39:24 -0800 Subject: [PATCH 09/19] BlockDiagram.drawio --- diagrams/Untitled Diagram.drawio | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/diagrams/Untitled Diagram.drawio b/diagrams/Untitled Diagram.drawio index f812011..7a9761a 100644 --- a/diagrams/Untitled Diagram.drawio +++ b/diagrams/Untitled Diagram.drawio @@ -1 +1,13 @@ -UzV2zq1wL0osyPDNT0nNUTV2VTV2LsrPL4GwciucU3NyVI0MMlNUjV1UjYwMgFjVyA2HrCFY1qAgsSg1rwSLBiADYTaQg2Y1AA== \ No newline at end of file + + + + + + + + + + + + + From 13e4b542e0fc42f8e44c1138dd47fbeb3dd01cf5 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Sat, 4 Feb 2023 16:40:54 -0800 Subject: [PATCH 10/19] Update Untitled Diagram.drawio --- diagrams/Untitled Diagram.drawio | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/diagrams/Untitled Diagram.drawio b/diagrams/Untitled Diagram.drawio index 7a9761a..aa1b336 100644 --- a/diagrams/Untitled Diagram.drawio +++ b/diagrams/Untitled Diagram.drawio @@ -1,11 +1,11 @@ - + - + From 43d5f69221c4f472e630884e6be2e3c33e1fb539 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Mon, 6 Feb 2023 14:26:00 -0800 Subject: [PATCH 11/19] First draft of Specs and some minor updates --- CALL.md | 6 ++-- README.md | 2 +- SPECS.md | 28 ++++++++++++++++-- diagrams/README.md | 1 - .../.$block_diagram.drawio.bkp | 0 figures/block_diagram.drawio | 1 + figures/block_diagram.png | Bin 0 -> 59851 bytes overview.png => figures/overview.png | Bin 8 files changed, 31 insertions(+), 7 deletions(-) delete mode 100644 diagrams/README.md rename diagrams/Untitled Diagram.drawio => figures/.$block_diagram.drawio.bkp (100%) create mode 100644 figures/block_diagram.drawio create mode 100644 figures/block_diagram.png rename overview.png => figures/overview.png (100%) diff --git a/CALL.md b/CALL.md index f8b84e7..c57390b 100644 --- a/CALL.md +++ b/CALL.md @@ -1,11 +1,11 @@ ## 2023 SSCS “PICO” Open-Source Chipathon -### – Submission deadline: May 1, 2023 – +### – Submission deadline: May 1, 2023 – -The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. +The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. The goal of this chipathon is to bring together IC design newbies, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the rapidly growing open-source IC design movement. In contrast to previous chipathon editions (which were open-ended), this year’s goal is to create a specific set of building blocks that can be re-used to benefit the community as a whole. The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/). - + diff --git a/README.md b/README.md index 1341e9d..48838fb 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # SSCS “PICO” Open-Source Chipathon - + diff --git a/SPECS.md b/SPECS.md index fdf2da8..dc7cbb9 100644 --- a/SPECS.md +++ b/SPECS.md @@ -1,6 +1,30 @@ +# Specifications + +The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage. + + + +To our knowledge, there aren't any published prior-art designs that we can build on. However, we can draw some inspiration from a similar system that was designed for discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. + +What follows below are initial thoughts and minimum specs for each one of our major system components. All teams are encouraged to exceed the minimum requirements and explore what is possible! + +**1. Scope MUX and signal conditioning** +The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. + +| Specification | Symbol | Baseline requirement | Comment | +| ------------- | ------ |--------------------- |-------- | +| Scope input capacitance | Cin | <5pF | From each diff. input to ground +| Number of differential input channels | N | >=8 +| Noise | Neq | <0.5 LSBrms | Contribution of the front-end to the ADC's sampled noise -https://digilent.com/reference/test-and-measurement/analog-discovery-2/start +**2. AWG MUX and signal conditioning** -https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide +**3. Clock generator** +**4. ADCs** + +**5. DACs** + +**6. Digital interface** +One of the primary goals here is to enable a convenient USB interface to a host computer. Teams working on this aspect should design both the on- and off-chip digital circuitry. For the off-chip board, we can consider the lowest cost boards from [Digilent](https://digilent.com/shop/boards-and-components/system-boards/introductory-boards/?sort=priceasc). The USB UART provided [here](https://github.com/ricynlee/cmod-a7-uart-sram-test) could be useful for establishing the communication. diff --git a/diagrams/README.md b/diagrams/README.md deleted file mode 100644 index 8b13789..0000000 --- a/diagrams/README.md +++ /dev/null @@ -1 +0,0 @@ - diff --git a/diagrams/Untitled Diagram.drawio b/figures/.$block_diagram.drawio.bkp similarity index 100% rename from diagrams/Untitled Diagram.drawio rename to figures/.$block_diagram.drawio.bkp diff --git a/figures/block_diagram.drawio b/figures/block_diagram.drawio new file mode 100644 index 0000000..174e849 --- /dev/null +++ b/figures/block_diagram.drawio @@ -0,0 +1 @@ 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figures/overview.png From fc0520908f32690837b93954295115ca5957f550 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Mon, 6 Feb 2023 14:27:42 -0800 Subject: [PATCH 12/19] Update SPECS.md --- SPECS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SPECS.md b/SPECS.md index dc7cbb9..0aaf99c 100644 --- a/SPECS.md +++ b/SPECS.md @@ -1,6 +1,6 @@ # Specifications -The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage. +The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of a Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage. From 77ffb9141bde01fe68b8ccc40798f16d4d944ecb Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Mon, 6 Feb 2023 14:28:58 -0800 Subject: [PATCH 13/19] Update SPECS.md --- SPECS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SPECS.md b/SPECS.md index 0aaf99c..0f7020c 100644 --- a/SPECS.md +++ b/SPECS.md @@ -9,7 +9,7 @@ To our knowledge, there aren't any published prior-art designs that we can build What follows below are initial thoughts and minimum specs for each one of our major system components. All teams are encouraged to exceed the minimum requirements and explore what is possible! **1. Scope MUX and signal conditioning** -The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. +The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | From 9d3922d2bc3260d4085429fbf740287d40e002cd Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Mon, 6 Feb 2023 14:30:20 -0800 Subject: [PATCH 14/19] Update SPECS.md --- SPECS.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SPECS.md b/SPECS.md index 0f7020c..08dcdfd 100644 --- a/SPECS.md +++ b/SPECS.md @@ -1,4 +1,4 @@ -# Specifications +# Target specifications The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of a Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage. From f82681aa541c73c0b9842423f4a6dcb1e1fde52f Mon Sep 17 00:00:00 2001 From: Mehdi Saligane <48068702+msaligane@users.noreply.github.com> Date: Mon, 6 Feb 2023 20:58:10 -0500 Subject: [PATCH 15/19] Update SPECS.md --- SPECS.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/SPECS.md b/SPECS.md index 08dcdfd..2b2b348 100644 --- a/SPECS.md +++ b/SPECS.md @@ -2,7 +2,9 @@ The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of a Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage. - +

+ +

To our knowledge, there aren't any published prior-art designs that we can build on. However, we can draw some inspiration from a similar system that was designed for discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. From 9e08b74f968929c71db5bde2fea5097c5055f33b Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Tue, 7 Feb 2023 14:42:33 -0800 Subject: [PATCH 16/19] Updated specs --- .vscode/settings.json | 8 ++++++++ SPECS.md | 41 ++++++++++++++++++++++++++++++++++++----- 2 files changed, 44 insertions(+), 5 deletions(-) create mode 100644 .vscode/settings.json diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..db1e382 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,8 @@ +{ + "cSpell.words": [ + "Intermodulation", + "Nyquist", + "tapeouts", + "transimpedance" + ] +} \ No newline at end of file diff --git a/SPECS.md b/SPECS.md index 2b2b348..35763a6 100644 --- a/SPECS.md +++ b/SPECS.md @@ -6,27 +6,58 @@ The purpose of this page is to seed some ideas on what the “lab bench on a ch

-To our knowledge, there aren't any published prior-art designs that we can build on. However, we can draw some inspiration from a similar system that was designed for discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. +To our knowledge, there aren't any published prior-art “lab bench on a chip” designs that we can build on. However, we can draw some inspiration from a similar system that was designed for and with discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. -What follows below are initial thoughts and minimum specs for each one of our major system components. All teams are encouraged to exceed the minimum requirements and explore what is possible! +Generally, think of this entire project is an experiment. We want to explore what a team of enthusiasts, spread across the globe, can do within the new environment of open-source IC design. Even if we don't succeed at building the complete target system in our first attempt, the community can re-use the various blocks that we design for future iterations or for an entirely different purpose. + +What follows below are initial thoughts and baseline specs for each one of our major system components. All teams are encouraged to exceed these requirements and explore what is possible! **1. Scope MUX and signal conditioning** -The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. +The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements. The Analog Discovery 2 has adjustable offsets in each channel. This may not be needed for our design. | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | | Scope input capacitance | Cin | <5pF | From each diff. input to ground -| Number of differential input channels | N | >=8 +| Number of differential input channels | N | $\geq8$ | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks +| Programmable gain | G | 0.25, 0.5, 1, 2, 4, 8 | Gain <1 needed since ADC likely cannot handle rail-to-rail inputs +| Bandwidth | BW | Maximize | Should be linked to ADC's acquisition bandwidth | Noise | Neq | <0.5 LSBrms | Contribution of the front-end to the ADC's sampled noise **2. AWG MUX and signal conditioning** +The arbitrary waveform generator design should have an output MUX that allows the macro's user to direct the DAC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail outputs. The MUX resistance will limit the AWG drive strength, but this should be OK for small on-chip loads. + +| Specification | Symbol | Baseline requirement | Comment | +| ------------- | ------ |--------------------- |-------- | +| Max. AWG load capacitance | CL | 10pF | Driver stability must be ensured up to this level +| Number of differential input channels | N | $\geq8$ | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks +| Bandwidth | BW | Maximize | Should be linked to DAC's Nyquist bandwidth +| Slew rate | SR | $\geq V_{peak}\cdot 2\pi BW$ | Align with bandwidth, assuming largest supported signal +| Output noise | PSD | <20nV/rt-Hz | **3. Clock generator** +The clock generator(s) for both the ADC and DAC should be designed in alignment with the target specs for these converters. For example, the clock generator's jitter should not lead to a significant SNR degradation at the maximum input frequency. **4. ADCs** +The ADC and DAC design tasks wil likely the most challenging and time consuming. An important objective is to minimize silicon area while still achieving attractive specs for the given application. Teams working on this block should consider re-using existing designs, as for instance this [12-bit SAR ADC](https://github.com/w32agobot/SKY130_SAR-ADC). It is desirable to have at least two ADCs (as shown in the system diagram) so that two signals can be measured simultaneously in real time, but this is not a must. + +| Specification | Symbol | Baseline requirement | Comment | +| ------------- | ------ |--------------------- |-------- | +| Sampling rate | fs | $\geq$ 1.5MS/s | +| Effective number of bits | ENOB | $\geq9$ | Measured near Nyquist +| Input capacitance | Cin | $\leq$ 5pF | + **5. DACs** +For the DAC, it may be best to aim for a current steering topology (also used in the Analog Discovery 2). Such a DAC will produce a differential output current that is converted to a differential voltage and image-filtered by the AWG signal conditioning block. Off the shelf current steering DACs are typically designed for high currents to interface with 50 Ohm loads. This is not a requirement in our on-chip environment; we can deviate to minimize circuit area. + +| Specification | Symbol | Baseline requirement | Comment | +| ------------- | ------ |--------------------- |-------- | +| Update rate | fs | $\geq$ 10MS/s | +| Number of bits | B | $\geq$ 10 | +| Intermodulation distortion | IM3 | $\geq$ -60dB | Measured near Nyquist +| Noise spectral density | NSD | | To be aligned with overall PSD spec for the AWG path + **6. Digital interface** -One of the primary goals here is to enable a convenient USB interface to a host computer. Teams working on this aspect should design both the on- and off-chip digital circuitry. For the off-chip board, we can consider the lowest cost boards from [Digilent](https://digilent.com/shop/boards-and-components/system-boards/introductory-boards/?sort=priceasc). The USB UART provided [here](https://github.com/ricynlee/cmod-a7-uart-sram-test) could be useful for establishing the communication. +One of the primary goals here is to enable a convenient USB interface to a host computer. Teams working on this aspect should design both the on- and off-chip digital circuitry. For the off-chip board, we can consider the lowest cost boards from [Digilent](https://digilent.com/shop/boards-and-components/system-boards/introductory-boards/?sort=priceasc). The USB UART provided [here](https://github.com/ricynlee/cmod-a7-uart-sram-test) could be useful for establishing the communication. \ No newline at end of file From 79cf5e51cc9da759991854c16d21af6087c2306d Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Tue, 7 Feb 2023 15:00:39 -0800 Subject: [PATCH 17/19] Updated block diagram --- SPECS.md | 2 +- figures/.$block_diagram.drawio.bkp | 13 ------------- figures/block_diagram.drawio | 2 +- figures/block_diagram.png | Bin 59851 -> 0 bytes figures/block_diagram.svg | 4 ++++ 5 files changed, 6 insertions(+), 15 deletions(-) delete mode 100644 figures/.$block_diagram.drawio.bkp delete mode 100644 figures/block_diagram.png create mode 100644 figures/block_diagram.svg diff --git a/SPECS.md b/SPECS.md index 35763a6..73d4b5b 100644 --- a/SPECS.md +++ b/SPECS.md @@ -3,7 +3,7 @@ The purpose of this page is to seed some ideas on what the “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of a Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage.

- +

To our knowledge, there aren't any published prior-art “lab bench on a chip” designs that we can build on. However, we can draw some inspiration from a similar system that was designed for and with discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. diff --git a/figures/.$block_diagram.drawio.bkp b/figures/.$block_diagram.drawio.bkp deleted file mode 100644 index aa1b336..0000000 --- a/figures/.$block_diagram.drawio.bkp +++ /dev/null @@ -1,13 +0,0 @@ - - - - - - - - - - - - - diff --git a/figures/block_diagram.drawio b/figures/block_diagram.drawio index 174e849..efd5321 100644 --- a/figures/block_diagram.drawio +++ b/figures/block_diagram.drawio @@ -1 +1 @@ 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b/figures/block_diagram.svg @@ -0,0 +1,4 @@ + + + +
MUX
MUX
Scope Signal Conditioning
Scope Signal C...
N differential scope inputs
N differential...
ADC
ADC
Signal Conditioning
Signal Conditi...
ADC
ADC
FPGA board
FPGA board
USB
USB
On chip
On chip
Clock generator
Clock gener...
1
1
4
4
3
3
MUX
MUX
Scope Signal Conditioning
Scope Signal C...
N differential AWG outputs
N differential...
DAC
DAC
AWG Signal Conditioning
AWG Signal Con...
DAC
DAC
2
2
5
5
Data buffers
 & interface
Data buffers...
6
6
Off chip
Off chipText is not SVG - cannot display \ No newline at end of file From 3096ccce56edaa6e3210788fa54ee3ee1667ea6d Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Tue, 7 Feb 2023 15:07:01 -0800 Subject: [PATCH 18/19] Update SPECS.md --- SPECS.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/SPECS.md b/SPECS.md index 73d4b5b..bf77171 100644 --- a/SPECS.md +++ b/SPECS.md @@ -6,7 +6,7 @@ The purpose of this page is to seed some ideas on what the “lab bench on a ch

-To our knowledge, there aren't any published prior-art “lab bench on a chip” designs that we can build on. However, we can draw some inspiration from a similar system that was designed for and with discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. +To our knowledge, there aren't any published prior-art “lab bench on a chip” designs that we can build on. However, we can draw some inspiration from a similar system that was designed for PCB measurements. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal. Generally, think of this entire project is an experiment. We want to explore what a team of enthusiasts, spread across the globe, can do within the new environment of open-source IC design. Even if we don't succeed at building the complete target system in our first attempt, the community can re-use the various blocks that we design for future iterations or for an entirely different purpose. @@ -17,7 +17,7 @@ The oscilloscope design should have an input MUX that allows the macro's user to | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | -| Scope input capacitance | Cin | <5pF | From each diff. input to ground +| Scope input capacitance | Cin | < 5pF | From each diff. input to ground | Number of differential input channels | N | $\geq8$ | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks | Programmable gain | G | 0.25, 0.5, 1, 2, 4, 8 | Gain <1 needed since ADC likely cannot handle rail-to-rail inputs | Bandwidth | BW | Maximize | Should be linked to ADC's acquisition bandwidth @@ -25,11 +25,11 @@ The oscilloscope design should have an input MUX that allows the macro's user to **2. AWG MUX and signal conditioning** -The arbitrary waveform generator design should have an output MUX that allows the macro's user to direct the DAC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail outputs. The MUX resistance will limit the AWG drive strength, but this should be OK for small on-chip loads. +The arbitrary waveform generator design should have an output MUX that allows the macro's user to direct the DAC resources to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail outputs. The MUX resistance will limit the AWG drive strength, but this should be OK for small on-chip loads. The Analog Discovery 2 has adjustable offsets in each channel. This may not be needed for our design. | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | -| Max. AWG load capacitance | CL | 10pF | Driver stability must be ensured up to this level +| AWG load capacitance | CL | $\leq$ 10pF | Driver stability must be ensured up to this level | Number of differential input channels | N | $\geq8$ | For a future project, much larger N could be beneficial for enabling "tiny tapeouts" for analog circuits with many small blocks | Bandwidth | BW | Maximize | Should be linked to DAC's Nyquist bandwidth | Slew rate | SR | $\geq V_{peak}\cdot 2\pi BW$ | Align with bandwidth, assuming largest supported signal @@ -39,7 +39,7 @@ The arbitrary waveform generator design should have an output MUX that allows th The clock generator(s) for both the ADC and DAC should be designed in alignment with the target specs for these converters. For example, the clock generator's jitter should not lead to a significant SNR degradation at the maximum input frequency. **4. ADCs** -The ADC and DAC design tasks wil likely the most challenging and time consuming. An important objective is to minimize silicon area while still achieving attractive specs for the given application. Teams working on this block should consider re-using existing designs, as for instance this [12-bit SAR ADC](https://github.com/w32agobot/SKY130_SAR-ADC). It is desirable to have at least two ADCs (as shown in the system diagram) so that two signals can be measured simultaneously in real time, but this is not a must. +The ADC and DAC design tasks will likely the most challenging and time consuming. An important objective is to minimize silicon area while still achieving attractive specs for the given application. Teams working on this block should consider re-using existing designs, as for instance this [12-bit SAR ADC](https://github.com/w32agobot/SKY130_SAR-ADC). It is desirable to have at least two ADCs (as shown in the system diagram) so that two signals can be measured simultaneously in real time, but this is not a must. | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | @@ -49,7 +49,7 @@ The ADC and DAC design tasks wil likely the most challenging and time consuming. **5. DACs** -For the DAC, it may be best to aim for a current steering topology (also used in the Analog Discovery 2). Such a DAC will produce a differential output current that is converted to a differential voltage and image-filtered by the AWG signal conditioning block. Off the shelf current steering DACs are typically designed for high currents to interface with 50 Ohm loads. This is not a requirement in our on-chip environment; we can deviate to minimize circuit area. +For the DAC, it may be best to aim for a current steering topology (also used in the Analog Discovery 2). Such a DAC will produce a differential output current that is converted to a differential voltage and image-filtered by the AWG signal conditioning block. Off the shelf current steering DACs are typically designed for high currents to interface with 50 Ohm loads. This is not a requirement in our on-chip environment; we can deviate to minimize circuit area. It is desirable to have at least two DACs (as shown in the system diagram) so that two signals can be generated simultaneously in real time, but this is not a must. | Specification | Symbol | Baseline requirement | Comment | | ------------- | ------ |--------------------- |-------- | From ce4acb191d65395cfd03e7aa6b8452129e425020 Mon Sep 17 00:00:00 2001 From: Boris Murmann <62622760+bmurmann@users.noreply.github.com> Date: Tue, 7 Feb 2023 15:11:10 -0800 Subject: [PATCH 19/19] Update FAQ.md --- FAQ.md | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/FAQ.md b/FAQ.md index b64f20e..f6af9ab 100644 --- a/FAQ.md +++ b/FAQ.md @@ -1,25 +1,16 @@ # FAQ Q: Do I need to be an IEEE SSCS member to participate? -A: No, but you are encouraged to join and benefit from our broad range of resources. Please refer to this link. +A: No, but you are encouraged to join and benefit from our broad range of resources. Please refer to this [link](https://sscs.ieee.org/membership). Q: May I re-use someone else’s open-source design? A: Yes! Please be sure to give credit to the original contributor. Q: Does my design need to be open-source? -A: Yes. Your design must be posted on a git-compatible repo and be publicly accessible. The project top-level must include a license file for an approved open-source license agreement (we recommend using the Apache-2.0 license). Third-party source code must be identified, and source code must contain proper headers. Refer to the Open MPW Shuttle Program FAQ for further guidance. +A: Yes. Your design must be posted on a git-compatible repo and be publicly accessible. The project top-level must include a license file for an approved open-source license agreement (we recommend using the Apache-2.0 license). Third-party source code must be identified, and source code must contain proper headers. Q: What is the purpose of the planned online meetups? -A: We will use these meetings for project presentations, networking among teams, short lectures on various circuit design topics, tool support as well as any other topic that will help you learn and succeed! +A: We will use these meetings for project presentations, networking among teams, short lectures on various circuit design topics, tool support as well as any other topic that will help us learn and succeed! -Q: What happens if I am selected, but cannot finish my design by the chipathon’s tapeout deadline? -A: You can participate in a later Google-sponsored Open-MPW run. - -Q: Will I be able to allocate a full 10 mm2 Caravel seat for my tapeout? -A: It is possible, but will depend on the size of your block. We will try to combine a number of blocks to maximize chip area utilization and to create useful subsystems (for example, ADC combined with a reference generator). We will use the meetups to plan possible design mergers. - -Q: Will all selected teams be able to tape out? -A: We will perform design status audits before the tapeout and may only advance a subset of the designs based on their readiness. - -Q: I am not a participating designer, but would like to contribute as a volunteer/mentor, is this possible? +Q: I would like to contribute as a volunteer/mentor, is this possible? A: Yes! Please sign up [here](https://sscs.ieee.org/volunteer-opportunities#SSCD).