* CDAC Simulation

.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical

*.option method = gear

.param width=2.4u

* Voltage sources definition
.param vh=3.3
.param timescale=1m

VCC ref 0 3.3
VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale})
VD4 d4 0 PULSE(0 {vh} {4*timescale} 1p 1p {17*timescale} {25*timescale})
VD5 d5 0 PULSE(0 {vh} {5*timescale} 1p 1p {15*timescale} {25*timescale})
VD6 d6 0 PULSE(0 {vh} {6*timescale} 1p 1p {13*timescale} {25*timescale})
VD7 d7 0 PULSE(0 {vh} {7*timescale} 1p 1p {11*timescale} {25*timescale})
VD8 d8 0 PULSE(0 {vh} {8*timescale} 1p 1p {9*timescale} {25*timescale})
VD9 d9 0 PULSE(0 {vh} {9*timescale} 1p 1p {7*timescale} {25*timescale})
VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale})

* inv: Inverter
.subckt inv high low in out
XQP out in high high pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQN out in low  low  nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
.ends inverter

* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
XI1 ref_a ref_b in     in_neg inv
XI2 ref_a ref_b in_neg sw_out inv
XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
.ends cdac_line

* Components
.param cu=5u
XC0 0    outl mim_1p5fF c_width={sqrt(1)*cu}   c_length={sqrt(1)*cu}   m=1
XCA outl outr mim_1p5fF c_width={sqrt(1)*cu}   c_length={sqrt(1)*cu}   m=1
RCA outl outr 100T
XD1  d1  outl ref 0 cdac_line c_width={sqrt(1)*cu}  c_length={sqrt(1)*cu}
XD2  d2  outl ref 0 cdac_line c_width={sqrt(2)*cu}  c_length={sqrt(2)*cu}
XD3  d3  outl ref 0 cdac_line c_width={sqrt(4)*cu}  c_length={sqrt(4)*cu}
XD4  d4  outl ref 0 cdac_line c_width={sqrt(8)*cu}  c_length={sqrt(8)*cu}
XD5  d5  outl ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
XD6  d6  outl ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
XD7  d7  outr ref 0 cdac_line c_width={sqrt(1)*cu}  c_length={sqrt(1)*cu}
XD8  d8  outr ref 0 cdac_line c_width={sqrt(2)*cu}  c_length={sqrt(2)*cu}
XD9  d9  outr ref 0 cdac_line c_width={sqrt(4)*cu}  c_length={sqrt(4)*cu}
XD10 d10 outr ref 0 cdac_line c_width={sqrt(8)*cu}  c_length={sqrt(8)*cu}
XD11 d11 outr ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}

.include "param.spice"

.op
.option post nomod
.end

.tran 10u {stoptime} uic

.control
run
set wr_singlescale
wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
.endc