51 lines
1.7 KiB
Plaintext
51 lines
1.7 KiB
Plaintext
* CDAC Simulation
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.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
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.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
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.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
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.param width=10u
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* Voltage sources definition
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.param vh=3.3
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.param timescale=0.1
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VCC ref 0 5
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VD1 d1 0 PULSE(0 {vh} {0*timescale} 1p 1p {11*timescale} {12*timescale})
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VD2 d2 0 PULSE(0 {vh} {1*timescale} 1p 1p {9*timescale} {12*timescale})
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VD3 d3 0 PULSE(0 {vh} {2*timescale} 1p 1p {7*timescale} {12*timescale})
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VD4 d4 0 PULSE(0 {vh} {3*timescale} 1p 1p {5*timescale} {12*timescale})
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VD5 d5 0 PULSE(0 {vh} {4*timescale} 1p 1p {3*timescale} {12*timescale})
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VD6 d6 0 PULSE(0 {vh} {5*timescale} 1p 1p {1*timescale} {12*timescale})
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* cdac_line: Capacitor controlled by switch
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.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
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XQN sw_out in ref_a sw_out nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
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XQP sw_out in ref_b ref_b pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
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XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
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.ends cdac_line
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* Components
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XC0 0 out mim_1p5fF c_width=5u c_length=5u m=1
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XD1 d1 out ref 0 cdac_line
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XD2 d2 out ref 0 cdac_line
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XD3 d3 out ref 0 cdac_line
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XD4 d4 out ref 0 cdac_line
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XD5 d5 out ref 0 cdac_line
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XD6 d6 out ref 0 cdac_line
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XD7 d7 out ref 0 cdac_line
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XD8 d8 out ref 0 cdac_line
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XD9 d9 out ref 0 cdac_line
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XD10 d10 out ref 0 cdac_line
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XD11 d11 out ref 0 cdac_line
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XD12 d12 out ref 0 cdac_line
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.op
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.option post nomod
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.end
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.control
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tran 1m 3.2 uic
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set wr_singlescale
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wrdata output.txt V(out) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6)
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.endc |