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Add PDK and CDAC simulation

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Mario Romero 2023-04-26 22:47:40 -04:00
parent 97a2c475a9
commit 9b76362941
3 changed files with 55 additions and 0 deletions
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.gitmodules vendored Normal file
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[submodule "gf180mcu-pdk"]
path = gf180mcu-pdk
url = https://github.com/google/gf180mcu-pdk.git

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gf180mcu-pdk Submodule

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Subproject commit e1531ba651a722b9768cea073f46cd85118033c5

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spice/cdac.spice Normal file
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* CDAC Simulation
.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
.param width=10u
* Voltage sources definition
.param vh=3.3
.param timescale=0.1
VCC ref 0 5
VD1 d1 0 PULSE(0 {vh} {0*timescale} 1p 1p {11*timescale} {12*timescale})
VD2 d2 0 PULSE(0 {vh} {1*timescale} 1p 1p {9*timescale} {12*timescale})
VD3 d3 0 PULSE(0 {vh} {2*timescale} 1p 1p {7*timescale} {12*timescale})
VD4 d4 0 PULSE(0 {vh} {3*timescale} 1p 1p {5*timescale} {12*timescale})
VD5 d5 0 PULSE(0 {vh} {4*timescale} 1p 1p {3*timescale} {12*timescale})
VD6 d6 0 PULSE(0 {vh} {5*timescale} 1p 1p {1*timescale} {12*timescale})
* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
XQN sw_out in ref_a sw_out nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQP sw_out in ref_b ref_b pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
.ends cdac_line
* Components
XC0 0 out mim_1p5fF c_width=5u c_length=5u m=1
XD1 d1 out ref 0 cdac_line
XD2 d2 out ref 0 cdac_line
XD3 d3 out ref 0 cdac_line
XD4 d4 out ref 0 cdac_line
XD5 d5 out ref 0 cdac_line
XD6 d6 out ref 0 cdac_line
XD7 d7 out ref 0 cdac_line
XD8 d8 out ref 0 cdac_line
XD9 d9 out ref 0 cdac_line
XD10 d10 out ref 0 cdac_line
XD11 d11 out ref 0 cdac_line
XD12 d12 out ref 0 cdac_line
.op
.option post nomod
.end
.control
tran 1m 3.2 uic
set wr_singlescale
wrdata output.txt V(out) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6)
.endc