Mario1159/sscs-chipathon-sar-adc
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Update verilog simulation

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This commit is contained in:
Mario Romero 2023-05-05 20:27:34 -04:00
parent c27dcf3366
commit e3a31657cc
2 changed files with 17 additions and 8 deletions
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12
verilog/rtl/Code_Register.v
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@ -31,13 +31,13 @@ always @(posedge shift_register_out[N_bits + 1] or posedge rst) begin
end end
always@ (posedge shift_register_out[0]) begin // always@ (posedge shift_register_out[0]) begin
if(rst) // if(rst)
data_register <= 'd0 ; // data_register <= 'd0 ;
else if (shift_register_out[0]) // else if (shift_register_out[0])
data_register<= 'd0 ; // data_register<= 'd0 ;
end // end
assign data_register_out =data_register [N_bits - 1 : 0] ; assign data_register_out =data_register [N_bits - 1 : 0] ;

13
verilog/tb/SAR_SIM.sv
View File

@ -44,6 +44,15 @@ always @(*) begin
end end
always @(*) begin
if (EOC) begin
reset = 'd1 ;
#1
reset = 'd0 ;
end
end
initial begin initial begin
clk_sar = 0 ; clk_sar = 0 ;
@ -52,7 +61,7 @@ initial begin
#2 #2
reset = 0 ; reset = 0 ;
#50 #100
$finish ; $finish ;
end end
@ -68,7 +77,7 @@ integer f , i ;
initial begin initial begin
f = $fopen("output.csv", "w"); f = $fopen("output.csv", "w");
$fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n"); $fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
for (i=0; i<50; i++) begin for (i=0; i<102; i++) begin
//$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out ); //$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
$fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] ); $fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
#1; #1;