From e3a31657ccb883999bbd844241714bb5168b83f7 Mon Sep 17 00:00:00 2001
From: Mario1159 <mario@1159.cl>
Date: Fri, 5 May 2023 20:27:34 -0400
Subject: [PATCH] Update verilog simulation

---
 verilog/rtl/Code_Register.v | 12 ++++++------
 verilog/tb/SAR_SIM.sv       | 13 +++++++++++--
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/verilog/rtl/Code_Register.v b/verilog/rtl/Code_Register.v
index 9142c04..2df4d6d 100644
--- a/verilog/rtl/Code_Register.v
+++ b/verilog/rtl/Code_Register.v
@@ -31,13 +31,13 @@ always @(posedge  shift_register_out[N_bits + 1] or posedge rst) begin
 
 end
 
-always@ (posedge shift_register_out[0]) begin 
-         if(rst)
-            data_register <= 'd0 ; 
-        else if (shift_register_out[0])
-             data_register<= 'd0 ; 
+// always@ (posedge shift_register_out[0]) begin 
+//          if(rst)
+//             data_register <= 'd0 ; 
+//         else if (shift_register_out[0])
+//              data_register<= 'd0 ; 
 
-end
+// end
 
 assign data_register_out =data_register [N_bits - 1 : 0] ; 
 
diff --git a/verilog/tb/SAR_SIM.sv b/verilog/tb/SAR_SIM.sv
index 7de270b..b8ed8e8 100644
--- a/verilog/tb/SAR_SIM.sv
+++ b/verilog/tb/SAR_SIM.sv
@@ -44,6 +44,15 @@ always @(*) begin
 
 end
 
+always @(*) begin
+    if (EOC) begin
+        reset = 'd1 ;
+        #1
+        reset = 'd0 ;
+    end
+
+end
+
 
 initial begin
     clk_sar = 0 ;
@@ -52,7 +61,7 @@ initial begin
     #2
     reset = 0 ;
 
-    #50
+    #100
     $finish ;
 
 end
@@ -68,7 +77,7 @@ integer  f , i ;
 initial begin
     f = $fopen("output.csv", "w");
     $fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
-    for (i=0; i<50; i++) begin 
+    for (i=0; i<102; i++) begin 
         //$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
         $fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
         #1;