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Add Register File

Mario Romero 2023-08-07 19:51:31 +00:00
parent e981894064
commit ac844a2fbf
1 changed files with 40 additions and 0 deletions
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# Register File
> *Defined in [rtl/register_file.sv](https://git.1159.cl/Mario1159/RVSCC/src/branch/main/rtl/register_file.sv.sv)*
<table>
<tr>
<th>Figure</th>
<th>Direction</th>
<th>Signal</th>
</tr>
<tr>
<td rowspan="8"></td>
<td rowspan="6">Input</td>
<td>clk</td>
</tr>
<tr>
<td>rst</td>
</tr>
<tr>
<td>addr_1</td>
</tr>
<tr>
<td>addr_2</td>
</tr>
<tr>
<td>addr_3</td>
</tr>
<tr>
<td>write_enable_3</td>
</tr>
<tr>
<td rowspan="2">Output</td>
<td>read_data_1</td>
</tr>
<tr>
<td>read_data_2</td>
</tr>
</table>
32-bit register container using synchronous reset and write_enable states.