24 lines
413 B
Systemverilog
24 lines
413 B
Systemverilog
`timescale 1ns / 1ps
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module Test_ImmExtend();
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logic[1:0] imm_src;
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logic[31:0] instr;
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logic[31:0] imm_ext;
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Extend imm_extend(
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.imm_src(imm_src),
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.instr(instr[31:7]),
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.imm_ext(imm_ext)
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);
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initial begin
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instr='h00a00893;
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#20
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imm_src='d0;
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#20
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imm_src='d1;
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#20
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imm_src='d2;
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end
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endmodule
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