Mario1159/RVSCC
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RISC-V Simple Core Collection
28 Commits 3 Branches 0 Tags 356 KiB
SystemVerilog 79.3%
CMake 14.4%
Assembly 2.6%
C++ 2.1%
Dockerfile 0.8%
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Mario Romero f4caab4e18 Update CPU
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fw Update test toolchain 2022-12-24 00:30:12 +00:00
rtl Update CPU 2022-12-23 22:13:40 -03:00
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README.md

README.md

5-Stage RISC-V pipelined processor with hazard detection