20 lines
434 B
Systemverilog
20 lines
434 B
Systemverilog
`timescale 1ns / 1ps
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module DataMemory #(
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parameter N = 32,
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parameter SIZE = 64)(
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input logic clk,
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input logic[N-1:0] addr,
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input logic write_enable,
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input logic[N-1:0] write_data,
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output logic[N-1:0] read_data
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);
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logic[N-1:0] mem[SIZE-1];
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always_ff @(posedge clk) begin
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if (write_enable)
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mem[addr] <= write_data;
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else
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read_data <= mem[addr];
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end
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endmodule |